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| REJ09B0394-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 TM SH7101 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7100 Series SH7101 HD6437101 Rev.2.00 Revision date: Sep. 27, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.2.00 Sep. 27, 2007 Page ii of xxxiv REJ09B0394-0200 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.2.00 Sep. 27, 2007 Page iii of xxxiv REJ09B0394-0200 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Index Rev.2.00 Sep. 27, 2007 Page iv of xxxiv REJ09B0394-0200 Preface The SH7101 single-chip RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: * Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification SH7101 (80-pin version) On-Chip ROM Classification Mask ROM version (ROM: 32 kbytes) Part No. HD6437101 In this manual, the product abbreviations are used to distinguish products. For example, products are collectively referred to as the SH7101. * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual. * In order to understand the details of a register when the user knows its name Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bit names, and initial values of the registers are summarized in section 18, List of Registers. Rev.2.00 Sep. 27, 2007 Page v of xxxiv REJ09B0394-0200 Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Bit order: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7101 manuals: Document Title SH7101 Hardware Manual SH-1/SH-2/SH-DSP Software Manual Document No. This manual REJ09B0171-0500 Users manuals for development tools: Document Title SuperH C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SuperH RISC engine Simulator/Debugger (for Windows) User's Manual High-performance Embedded Workshop User's Manual Document No. REJ10B0047-0100 REJ10B0210-0300 REJ10J1554-0100 Application Notes: Document Title SuperH RISC engine C/C++ Compiler Package Application Note Document No. REJ05B0463-0400 Rev.2.00 Sep. 27, 2007 Page vi of xxxiv REJ09B0394-0200 Main Revisions for This Edition Item All 6.5 Interrupt Exception Processing Vectors Table Table 6.2 Interrupt Exception Processing Vectors and Priorities Page 79 Revision (See Manual for Details) * Company name and brand names amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Table amended Interrupt Source Name TGIB_3 TGIC_3 TGID_3 TCIV_3 MTU channel 3 TGIA_3 7.5.1 Bus Control Register 1 (BCR1) 89 Bit table amended Bit 14 Bit Name Initial Value 1 R/W R Description Reserved These bits are always read as 1 and should always be written to 1. 8.1 Features Figure 8.1 Block Diagram of MTU 94 Title and figure amended Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TGI4C TGI4D TCI4V 8.3.3 Timer I/O Control 109 Register (TIOR) Table 8.13 TIORL_0 (channel 0) Table amended Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 TGRC_0 Function Output compare register* TIOC0C Pin Function Output disable Initial output is 0 0 output at compare match 8.4.4 Cascaded Operation Table 8.30 Cascaded Combinations 149 Note amended Note: When phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and the counters operates independently in phase counting mode. Rev.2.00 Sep. 27, 2007 Page vii of xxxiv REJ09B0394-0200 Item 8.4.4 Cascaded Operation Figure 8.18 Cascaded Operation Setting Procedure 8.4.8 Complementary PWM Mode Example of Complementary PWM Mode Setting Procedure: Page 149 Revision (See Manual for Details) Figure amended [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'111 to select TCNT_2 overflow/ underflow counting. 170 Description amended 10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). 11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Description amended * Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller's bus control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to the mode registers, control registers, and counters. In access disabled state, an undefined value is read from the registers concerned, and cannot be modified. Description amended An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one each for channels 1 and 2. Complementary PWM 192 Mode Output Protection Function: 8.5.1 Interrupts and Priorities Underflow Interrupt: 194 Rev.2.00 Sep. 27, 2007 Page viii of xxxiv REJ09B0394-0200 Item Page Revision (See Manual for Details) Figure amended Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 8.7.15 Overflow Flags in 216 Reset Sync PWM Mode Figure 8.81 Reset Sync PWM Mode Overflow Flag H'0000 TCFV_3 TCFV_4 Not set Not set 8.7.21 Simultaneous 219 Input Capture of TCNT_1 and TCNT_2 in Cascade Connection Description amended When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. Rev.2.00 Sep. 27, 2007 Page ix of xxxiv REJ09B0394-0200 Item 8.9.5 Usage Note Page 262 Revision (See Manual for Details) Description added (1) Symptom (a) Regarding the POEnF*1 bits If setting of the POEnF bits in the input level control/status registers (ICSR1 and ICSR2) by the hardware*2 and reading from these bits occur simultaneously, "0" will be read, where "1" should be read. Furthermore, if clearing of these bits is attempted subsequent to the above condition, the clearing should be ignored*3 but it will be carried out. Notes: *1 For the SH7046-Series and SH7047-Series, n = 0 to 6; for the SH7144-Series, n = 0 to 3. *2 The POEnF bits are set when the signals input to the respective POEn pins satisfy the conditions that are specified by the POEnM1 and POEnM0 of the ICSR1 and ICSR2. *3 The correct operation is that clearing of the POEnF bits is only possible after "1" is read from them in order to prevent accidental clearing. (b) Regarding the OSF bit The same symptom applies to the OSF bits of the output level control/status register (OCSR). (2) To Avoid This Problem Please clear the POEnF bits or the OSF bit in these steps: first execute a read for ICSR1, ICSR2, or OCSR, then write "0" to the bits that had a read value of "1" to clear them while writing "1" to other bits. If this procedure is not followed, the POEnF bits and the OSF bit may be cleared unexpectedly if their setting by hardware and reading occur simultaneously. 10.3.2 Receive Data Register (RDR) 10.3.4 Transmit Data Register (TDR) 280 Description added ... RDR cannot be written to by the CPU. The initial value of RDR is H'00. 280 Description added ... Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF. Rev.2.00 Sep. 27, 2007 Page x of xxxiv REJ09B0394-0200 Item 11.1 Features Page 325 Revision (See Manual for Details) Description added * Conversion time: 6.7 s per channel (at P = 20-MHz operation) 5.4 s per channel (at P = 25-MHz operation) 11.7.2 Permissible Signal Source Impedance 340 Description amended This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less, or 3 k or less. This specification is provided to enable the A/D converter's sampleand-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k or 3 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. ... 17.3.1 Sleep Mode Notes on Using Sleep Mode 395 Description added * There are 4 conditions to clear sleep mode. (1) Clearing by an interrupt (2) Clearing by DTC address error (3) Clearing by the power-on reset (4) Clearing by the manual reset When clearing sleep mode by (1) or (2), CPU may run out of control. Please clear sleep mode by (3) or (4), don't use (1) or (2). * Do not use DTC module or AUD module during sleep mode. Rev.2.00 Sep. 27, 2007 Page xi of xxxiv REJ09B0394-0200 All trademarks and registered trademarks are the property of their respective owners. Rev.2.00 Sep. 27, 2007 Page xii of xxxiv REJ09B0394-0200 Contents Section 1 Overview............................................................................................... 1 1.1 1.2 1.3 1.4 1.5 Features .................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Arrangement .................................................................................................................... 4 Pin Functions ......................................................................................................................... 5 Differences from SH7046 Group ........................................................................................... 9 Section 2 CPU..................................................................................................... 11 2.1 2.2 Features ................................................................................................................................ 11 Register Configuration ......................................................................................................... 11 2.2.1 General Registers (Rn)............................................................................................ 13 2.2.2 Control Registers .................................................................................................... 13 2.2.3 System Registers ..................................................................................................... 14 2.2.4 Initial Values of Registers....................................................................................... 15 Data Formats ........................................................................................................................ 15 2.3.1 Data Format in Registers......................................................................................... 15 2.3.2 Data Formats in Memory ........................................................................................ 16 2.3.3 Immediate Data Format .......................................................................................... 16 Instruction Features.............................................................................................................. 17 2.4.1 RISC-Type Instruction Set...................................................................................... 17 2.4.2 Addressing Modes .................................................................................................. 20 2.4.3 Instruction Format................................................................................................... 24 Instruction Set ...................................................................................................................... 26 2.5.1 Instruction Set by Classification ............................................................................. 26 Processing States.................................................................................................................. 41 2.6.1 State Transitions...................................................................................................... 41 2.3 2.4 2.5 2.6 Section 3 MCU Operating Modes....................................................................... 43 3.1 3.2 3.3 Selection of Operating Modes.............................................................................................. 43 Input/Output Pins ................................................................................................................. 44 Explanation of Operating Modes ......................................................................................... 44 3.3.1 Mode 3 (Single chip mode)..................................................................................... 44 3.3.2 Clock Mode............................................................................................................. 44 Address Map ........................................................................................................................ 45 Initial State of This LSI........................................................................................................ 46 3.4 3.5 Section 4 Clock Pulse Generator ........................................................................ 47 4.1 Oscillator.............................................................................................................................. 47 Rev.2.00 Sep. 27, 2007 Page xiii of xxxiv REJ09B0394-0200 4.2 4.3 4.1.1 Connecting Crystal Resonator ................................................................................ 47 4.1.2 External Clock Input Method.................................................................................. 49 Function for Detecting Oscillator Halt................................................................................. 49 Usage Notes ......................................................................................................................... 50 4.3.1 Note on Crystal Resonator ...................................................................................... 50 4.3.2 Notes on Board Design ........................................................................................... 50 Section 5 Exception Processing...........................................................................53 5.1 Overview.............................................................................................................................. 53 5.1.1 Types of Exception Processing and Priority ........................................................... 53 5.1.2 Exception Processing Operations............................................................................ 54 5.1.3 Exception Processing Vector Table ........................................................................ 55 Resets ................................................................................................................................ 57 5.2.1 Types of Reset ........................................................................................................ 57 5.2.2 Power-On Reset ...................................................................................................... 57 5.2.3 Manual Reset .......................................................................................................... 58 Address Errors ..................................................................................................................... 59 5.3.1 Cause of Address Error Exception.......................................................................... 59 5.3.2 Address Error Exception Processing....................................................................... 60 Interrupts.............................................................................................................................. 60 5.4.1 Interrupt Sources..................................................................................................... 60 5.4.2 Interrupt Priority Level ........................................................................................... 61 5.4.3 Interrupt Exception Processing ............................................................................... 61 Exceptions Triggered by Instructions .................................................................................. 62 5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 62 5.5.2 Trap Instructions ..................................................................................................... 62 5.5.3 Illegal Slot Instructions ........................................................................................... 63 5.5.4 General Illegal Instructions..................................................................................... 63 Cases when Exception Sources are Not Accepted ............................................................... 64 5.6.1 Immediately after Delayed Branch Instruction ....................................................... 64 5.6.2 Immediately after Interrupt-Disabled Instruction ................................................... 64 Stack Status after Exception Processing Ends ..................................................................... 65 Usage Notes ......................................................................................................................... 66 5.8.1 Value of Stack Pointer (SP) .................................................................................... 66 5.8.2 Value of Vector Base Register (VBR) .................................................................... 66 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing......... 66 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Section 6 Interrupt Controller (INTC).................................................................67 6.1 6.2 Features................................................................................................................................ 67 Input/Output Pins ................................................................................................................. 68 Rev.2.00 Sep. 27, 2007 Page xiv of xxxiv REJ09B0394-0200 6.3 6.4 6.5 6.6 6.7 Register Descriptions ........................................................................................................... 68 6.3.1 Interrupt Control Register 1 (ICR1) ........................................................................ 69 6.3.2 Interrupt Control Register 2 (ICR2) ........................................................................ 70 6.3.3 IRQ Status Register (ISR)....................................................................................... 72 6.3.4 Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI) .................................. 73 Interrupt Sources .................................................................................................................. 75 6.4.1 External Interrupts .................................................................................................. 75 6.4.2 On-Chip Peripheral Module Interrupts ................................................................... 77 Interrupt Exception Processing Vectors Table..................................................................... 77 Operation.............................................................................................................................. 81 6.6.1 Interrupt Sequence .................................................................................................. 81 6.6.2 Stack after Interrupt Exception Processing ............................................................. 83 Interrupt Response Time ...................................................................................................... 84 Section 7 Bus State Controller (BSC)................................................................. 87 7.1 7.2 7.3 7.4 7.5 7.6 Features ................................................................................................................................ 87 Input/output Pin.................................................................................................................... 87 Register ................................................................................................................................ 87 Address Map ........................................................................................................................ 88 Register Description............................................................................................................. 89 7.5.1 Bus Control Register 1 (BCR1) .............................................................................. 89 On-chip Peripheral I/O Register Access .............................................................................. 90 Section 8 Multi-Function Timer Pulse Unit (MTU) ........................................... 91 8.1 8.2 8.3 Features ................................................................................................................................ 91 Input/Output Pins ................................................................................................................. 95 Register Descriptions ........................................................................................................... 96 8.3.1 Timer Control Register (TCR) ................................................................................ 98 8.3.2 Timer Mode Register (TMDR) ............................................................................. 102 8.3.3 Timer I/O Control Register (TIOR) ...................................................................... 104 8.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 122 8.3.5 Timer Status Register (TSR)................................................................................. 124 8.3.6 Timer Counter (TCNT)......................................................................................... 126 8.3.7 Timer General Register (TGR) ............................................................................. 127 8.3.8 Timer Start Register (TSTR)................................................................................. 127 8.3.9 Timer Synchro Register (TSYR) .......................................................................... 128 8.3.10 Timer Output Master Enable Register (TOER) .................................................... 130 8.3.11 Timer Output Control Register (TOCR) ............................................................... 131 8.3.12 Timer Gate Control Register (TGCR)................................................................... 133 8.3.13 Timer Subcounter (TCNTS) ................................................................................. 135 Rev.2.00 Sep. 27, 2007 Page xv of xxxiv REJ09B0394-0200 8.4 8.5 8.6 8.7 8.3.14 Timer Dead Time Data Register (TDDR)............................................................. 135 8.3.15 Timer Period Data Register (TCDR) .................................................................... 135 8.3.16 Timer Period Buffer Register (TCBR).................................................................. 135 8.3.17 Bus Master Interface ............................................................................................. 136 Operation ........................................................................................................................... 137 8.4.1 Basic Functions..................................................................................................... 137 8.4.2 Synchronous Operation......................................................................................... 142 8.4.3 Buffer Operation ................................................................................................... 145 8.4.4 Cascaded Operation .............................................................................................. 149 8.4.5 PWM Modes ......................................................................................................... 150 8.4.6 Phase Counting Mode........................................................................................... 156 8.4.7 Reset-Synchronized PWM Mode.......................................................................... 163 8.4.8 Complementary PWM Mode................................................................................ 167 Interrupt Sources................................................................................................................ 192 8.5.1 Interrupts and Priorities......................................................................................... 192 8.5.2 A/D Converter Activation..................................................................................... 194 Operation Timing............................................................................................................... 195 8.6.1 Input/Output Timing ............................................................................................. 195 8.6.2 Interrupt Signal Timing......................................................................................... 200 Usage Notes ....................................................................................................................... 204 8.7.1 Module Standby Mode Setting ............................................................................. 204 8.7.2 Input Clock Restrictions ....................................................................................... 204 8.7.3 Caution on Period Setting ..................................................................................... 205 8.7.4 Contention between TCNT Write and Clear Operations...................................... 205 8.7.5 Contention between TCNT Write and Increment Operations............................... 206 8.7.6 Contention between TGR Write and Compare Match .......................................... 207 8.7.7 Contention between Buffer Register Write and Compare Match ......................... 208 8.7.8 Contention between TGR Read and Input Capture............................................... 210 8.7.9 Contention between TGR Write and Input Capture.............................................. 211 8.7.10 Contention between Buffer Register Write and Input Capture ............................. 212 8.7.11 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 212 8.7.12 Counter Value during Complementary PWM Mode Stop .................................... 214 8.7.13 Buffer Operation Setting in Complementary PWM Mode ................................... 214 8.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 215 8.7.15 Overflow Flags in Reset Sync PWM Mode.......................................................... 216 8.7.16 Contention between Overflow/Underflow and Counter Clearing......................... 217 8.7.17 Contention between TCNT Write and Overflow/Underflow................................ 218 8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode........................................................................... 218 Rev.2.00 Sep. 27, 2007 Page xvi of xxxiv REJ09B0394-0200 8.8 8.9 8.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode........................................................................... 219 8.7.20 Interrupts in Module Standby Mode ..................................................................... 219 8.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection... 219 MTU Output Pin Initialization ........................................................................................... 220 8.8.1 Operating Modes................................................................................................... 220 8.8.2 Reset Start Operation ............................................................................................ 220 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. ................. 221 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. ................................................................ 222 Port Output Enable (POE).................................................................................................. 252 8.9.1 Features................................................................................................................. 252 8.9.2 Pin Configuration.................................................................................................. 254 8.9.3 Register Configuration.......................................................................................... 254 8.9.4 Operation .............................................................................................................. 259 8.9.5 Usage Note............................................................................................................ 262 Section 9 Watchdog Timer ............................................................................... 263 9.1 9.2 9.3 Features .............................................................................................................................. 263 Input/Output Pin................................................................................................................. 264 Register Descriptions ......................................................................................................... 265 9.3.1 Timer Counter (TCNT)......................................................................................... 265 9.3.2 Timer Control/Status Register (TCSR) ................................................................. 266 9.3.3 Reset Control/Status Register (RSTCSR) ............................................................. 268 Operation............................................................................................................................ 269 9.4.1 Watchdog Timer Mode ......................................................................................... 269 9.4.2 Interval Timer Mode ............................................................................................. 271 9.4.3 Clearing Software Standby Mode ......................................................................... 271 9.4.4 Timing of Setting the Overflow Flag (OVF) ........................................................ 272 9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)......................... 272 Interrupt Source.................................................................................................................. 273 Usage Notes ....................................................................................................................... 273 9.6.1 Notes on Register Access...................................................................................... 273 9.6.2 TCNT Write and Increment Contention................................................................ 275 9.6.3 Changing CKS2 to CKS0 Bit Values.................................................................... 275 9.6.4 Changing between Watchdog Timer/Interval Timer Modes................................. 275 9.6.5 System Reset by WDTOVF Signal....................................................................... 276 9.6.6 Internal Reset in Watchdog Timer Mode.............................................................. 276 9.6.7 Manual Reset in Watchdog Timer Mode .............................................................. 276 9.6.8 Notes on Using WDTOVF pin.............................................................................. 276 Rev.2.00 Sep. 27, 2007 Page xvii of xxxiv REJ09B0394-0200 9.4 9.5 9.6 Section 10 Serial Communication Interface (SCI) ............................................277 10.1 Features.............................................................................................................................. 277 10.2 Input/Output Pins ............................................................................................................... 279 10.3 Register Descriptions ......................................................................................................... 279 10.3.1 Receive Shift Register (RSR) ............................................................................... 280 10.3.2 Receive Data Register (RDR) ............................................................................... 280 10.3.3 Transmit Shift Register (TSR) .............................................................................. 280 10.3.4 Transmit Data Register (TDR).............................................................................. 280 10.3.5 Serial Mode Register (SMR) ................................................................................ 281 10.3.6 Serial Control Register (SCR)............................................................................... 283 10.3.7 Serial Status Register (SSR) ................................................................................. 285 10.3.8 Serial Direction Control Register (SDCR)............................................................ 287 10.3.9 Bit Rate Register (BRR) ....................................................................................... 287 10.4 Operation in Asynchronous Mode ..................................................................................... 296 10.4.1 Data Transfer Format............................................................................................ 296 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ......................................................................................... 298 10.4.3 Clock..................................................................................................................... 299 10.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 300 10.4.5 Data Transmission (Asynchronous Mode)............................................................ 301 10.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 303 10.5 Multiprocessor Communication Function.......................................................................... 307 10.5.1 Multiprocessor Serial Data Transmission ............................................................. 309 10.5.2 Multiprocessor Serial Data Reception .................................................................. 310 10.6 Operation in Clocked Synchronous Mode ......................................................................... 313 10.6.1 Clock..................................................................................................................... 313 10.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................. 314 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 315 10.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 318 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 320 10.7 Interrupts Sources .............................................................................................................. 322 10.7.1 Interrupts in Normal Serial Communication Interface Mode ............................... 322 10.8 Usage Notes ....................................................................................................................... 323 10.8.1 TDR Write and TDRE Flag .................................................................................. 323 10.8.2 Module Standby Mode Setting ............................................................................. 323 10.8.3 Break Detection and Processing (Asynchronous Mode Only).............................. 323 10.8.4 Sending a Break Signal (Asynchronous Mode Only) ........................................... 323 10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 324 Rev.2.00 Sep. 27, 2007 Page xviii of xxxiv REJ09B0394-0200 10.8.6 Cautions on Clocked Synchronous External Clock Mode .................................... 324 10.8.7 Caution on Clocked Synchronous Internal Clock Mode....................................... 324 Section 11 A/D Converter................................................................................. 325 11.1 Features .............................................................................................................................. 325 11.2 Input/Output Pins ............................................................................................................... 327 11.3 Register Descriptions ......................................................................................................... 328 11.3.1 A/D Data Registers 8 to 15 (ADDR8 to ADDR15) .............................................. 328 11.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) .................. 329 11.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1).................................. 330 11.3.4 A/D Trigger Select Register (ADTSR) ................................................................. 332 11.4 Operation............................................................................................................................ 333 11.4.1 Single Mode.......................................................................................................... 333 11.4.2 Continuous Scan Mode ......................................................................................... 333 11.4.3 Single-Cycle Scan Mode....................................................................................... 335 11.4.4 Input Sampling and A/D Conversion Time........................................................... 335 11.4.5 A/D Converter Activation by MTU ...................................................................... 337 11.4.6 External Trigger Input Timing .............................................................................. 337 11.5 Interrupt Sources ................................................................................................................ 338 11.6 Definitions of A/D Conversion Accuracy .......................................................................... 338 11.7 Usage Notes ....................................................................................................................... 340 11.7.1 Module Standby Mode Setting ............................................................................. 340 11.7.2 Permissible Signal Source Impedance .................................................................. 340 11.7.3 Influences on Absolute Accuracy ......................................................................... 340 11.7.4 Range of Analog Power Supply and Other Pin Settings ....................................... 341 11.7.5 Notes on Board Design ......................................................................................... 341 11.7.6 Notes on Noise Countermeasures ......................................................................... 341 Section 12 Compare Match Timer (CMT)........................................................ 343 12.1 Features .............................................................................................................................. 343 12.2 Register Descriptions ......................................................................................................... 344 12.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 344 12.2.2 Compare Match Timer Control/Status Register_0 and _1 (CMCSR_0, CMCSR_1) ...................................................................................... 345 12.2.3 Compare Match Timer Counter_0 and _1 (CMCNT_0, CMCNT_1)................... 346 12.2.4 Compare Match Timer Constant Register_0 and _1 (CMCOR_0, CMCOR_1)... 346 12.3 Operation............................................................................................................................ 346 12.3.1 Cyclic Count Operation ........................................................................................ 346 12.3.2 CMCNT Count Timing......................................................................................... 347 12.4 Interrupts ............................................................................................................................ 347 Rev.2.00 Sep. 27, 2007 Page xix of xxxiv REJ09B0394-0200 12.4.1 Interrupt Sources................................................................................................... 347 12.4.2 Compare Match Flag Set Timing.......................................................................... 347 12.4.3 Compare Match Flag Clear Timing ...................................................................... 348 12.5 Usage Notes ....................................................................................................................... 349 12.5.1 Contention between CMCNT Write and Compare Match.................................... 349 12.5.2 Contention between CMCNT Word Write and Incrementation ........................... 350 12.5.3 Contention between CMCNT Byte Write and Incrementation ............................. 351 Section 13 Pin Function Controller (PFC) ........................................................353 13.1 Register Descriptions ......................................................................................................... 360 13.1.1 Port A I/O Register L (PAIORL).......................................................................... 360 13.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1).................................. 361 13.1.3 Port B I/O Register (PBIOR) ................................................................................ 364 13.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)....................................... 365 13.1.5 Port E I/O Registers L and H (PEIORL and PEIORH)......................................... 366 13.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) ........ 366 13.2 Usage Notes ....................................................................................................................... 370 13.2.1 Note on PFC Setting ............................................................................................. 370 13.2.2 Note on PFC Setting Order ................................................................................... 370 Section 14 I/O Ports...........................................................................................371 14.1 Port A 14.1.1 14.1.2 14.2 Port B 14.2.1 14.2.2 14.3 Port E 14.3.1 14.3.2 14.4 Port F 14.4.1 14.4.2 14.5 Port G 14.5.1 14.5.2 .............................................................................................................................. 371 Register Description.............................................................................................. 372 Port A Data Register L (PADRL) ......................................................................... 372 .............................................................................................................................. 374 Register Description.............................................................................................. 374 Port B Data Register (PBDR) ............................................................................... 374 .............................................................................................................................. 376 Register Descriptions ............................................................................................ 377 Port E Data Registers H and L (PEDRH and PEDRL) ......................................... 377 .............................................................................................................................. 379 Register Description.............................................................................................. 379 Port F Data Register (PFDR) ................................................................................ 379 .............................................................................................................................. 381 Register Description.............................................................................................. 381 Port G Data Register (PGDR)............................................................................... 381 Section 15 Mask ROM ......................................................................................383 15.1 Usage Note......................................................................................................................... 383 Rev.2.00 Sep. 27, 2007 Page xx of xxxiv REJ09B0394-0200 Section 16 RAM ............................................................................................... 385 16.1 Usage Note......................................................................................................................... 385 Section 17 Power-Down Modes ....................................................................... 387 17.1 Input/Output Pins ............................................................................................................... 389 17.2 Register Descriptions ......................................................................................................... 390 17.2.1 Standby Control Register (SBYCR) ..................................................................... 390 17.2.2 System Control Register (SYSCR) ....................................................................... 392 17.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2).................. 393 17.3 Operation............................................................................................................................ 395 17.3.1 Sleep Mode ........................................................................................................... 395 17.3.2 Software Standby Mode........................................................................................ 396 17.3.3 Module Standby Mode.......................................................................................... 398 17.4 Usage Notes ....................................................................................................................... 399 17.4.1 I/O Port Status....................................................................................................... 399 17.4.2 Current Consumption during Oscillation Stabilization Wait Period ..................... 399 17.4.3 On-Chip Peripheral Module Interrupt................................................................... 399 17.4.4 Writing to MSTCR1 and MSTCR2 ...................................................................... 399 Section 18 List of Registers .............................................................................. 401 18.1 Register Addresses (Order of Address).............................................................................. 401 18.2 Register Bits....................................................................................................................... 408 18.3 Register States in Each Operating Mode............................................................................ 415 Section 19 Electrical Characteristics ................................................................ 421 19.1 Absolute Maximum Ratings .............................................................................................. 421 19.2 DC Characteristics ............................................................................................................. 422 19.3 AC Characteristics ............................................................................................................. 425 19.3.1 Test Conditions for the AC Characteristics........................................................... 425 19.3.2 Clock Timing ........................................................................................................ 426 19.3.3 Control Signal Timing .......................................................................................... 428 19.3.4 Multi-Function Timer Pulse Unit (MPU) Timing................................................. 431 19.3.5 I/O Port Timing..................................................................................................... 432 19.3.6 Watchdog Timer (WDT) Timing .......................................................................... 433 19.3.7 Serial Communication Interface (SCI) Timing ..................................................... 434 19.3.8 Output Enable (POE) Timing ............................................................................... 436 19.3.9 A/D Converter Timing .......................................................................................... 436 19.4 A/D Converter Characteristics ........................................................................................... 438 Appendix A Pin States ...................................................................................... 439 Rev.2.00 Sep. 27, 2007 Page xxi of xxxiv REJ09B0394-0200 Appendix B Product Lineup ..............................................................................441 Appendix C Package Dimensions .....................................................................443 Index .........................................................................................................445 Rev.2.00 Sep. 27, 2007 Page xxii of xxxiv REJ09B0394-0200 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of SH7101............................................................................ 3 Figure 1.2 SH7101 Pin Arrangement .......................................................................................... 4 Section 2 CPU Figure 2.1 CPU Internal Registers............................................................................................. 12 Figure 2.2 Data Format in Registers.......................................................................................... 15 Figure 2.3 Data Formats in Memory ......................................................................................... 16 Figure 2.4 Transitions between Processing States ..................................................................... 41 Section 3 MCU Operating Modes Figure 3.1 Address Map for SH7101 Mask ROM Version ....................................................... 45 Section 4 Clock Pulse Generator Figure 4.1 Block Diagram of Clock Pulse Generator ................................................................ 47 Figure 4.2 Connection of Crystal Resonator (Example)............................................................ 48 Figure 4.3 Crystal Resonator Equivalent Circuit ....................................................................... 48 Figure 4.4 Example of External Clock Connection ................................................................... 49 Figure 4.5 Cautions for Oscillator Circuit System Board Design.............................................. 50 Figure 4.6 Recommended External Circuitry around PLL ........................................................ 51 Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram ............................................................................................... 67 Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control................................................ 76 Figure 6.3 Interrupt Sequence Flowchart .................................................................................. 82 Figure 6.4 Stack after Interrupt Exception Processing .............................................................. 83 Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted.................. 85 Section 8 Multi-Function Timer Pulse Unit (MTU) Figure 8.1 Block Diagram of MTU ........................................................................................... 94 Figure 8.2 Complementary PWM Mode Output Level Example ............................................ 132 Figure 8.3 Example of Counter Operation Setting Procedure ................................................. 137 Figure 8.4 Free-Running Counter Operation ........................................................................... 138 Figure 8.5 Periodic Counter Operation.................................................................................... 139 Figure 8.6 Example of Setting Procedure for Waveform Output by Compare Match............. 139 Figure 8.7 Example of 0 Output/1 Output Operation .............................................................. 140 Figure 8.8 Example of Toggle Output Operation .................................................................... 140 Figure 8.9 Example of Input Capture Operation Setting Procedure ........................................ 141 Figure 8.10 Example of Input Capture Operation ..................................................................... 142 Figure 8.11 Example of Synchronous Operation Setting Procedure ......................................... 143 Figure 8.12 Example of Synchronous Operation....................................................................... 144 Rev.2.00 Sep. 27, 2007 Page xxiii of xxxiv REJ09B0394-0200 Figure 8.13 Figure 8.14 Figure 8.15 Figure 8.16 Figure 8.17 Figure 8.18 Figure 8.19 Figure 8.20 Figure 8.21 Figure 8.22 Figure 8.23 Figure 8.24 Figure 8.25 Figure 8.26 Figure 8.27 Figure 8.28 Figure 8.29 Figure 8.30 Figure 8.31 Figure 8.32 Figure 8.33 Figure 8.34 Figure 8.35 Figure 8.36 Figure 8.37 Figure 8.38 Figure 8.39 Figure 8.40 Figure 8.41 Figure 8.42 Figure 8.43 Figure 8.44 Figure 8.45 Figure 8.46 Figure 8.47 Figure 8.48 Figure 8.49 Figure 8.50 Figure 8.51 Compare Match Buffer Operation.......................................................................... 145 Input Capture Buffer Operation ............................................................................. 146 Example of Buffer Operation Setting Procedure.................................................... 146 Example of Buffer Operation (1) ........................................................................... 147 Example of Buffer Operation (2) ........................................................................... 148 Cascaded Operation Setting Procedure .................................................................. 149 Example of Cascaded Operation ............................................................................ 150 Example of PWM Mode Setting Procedure ........................................................... 152 Example of PWM Mode Operation (1) .................................................................. 153 Example of PWM Mode Operation (2) .................................................................. 154 Example of PWM Mode Operation (3) .................................................................. 155 Example of Phase Counting Mode Setting Procedure............................................ 157 Example of Phase Counting Mode 1 Operation ..................................................... 157 Example of Phase Counting Mode 2 Operation ..................................................... 158 Example of Phase Counting Mode 3 Operation ..................................................... 159 Example of Phase Counting Mode 4 Operation ..................................................... 160 Phase Counting Mode Application Example ......................................................... 162 Procedure for Selecting the Reset-Synchronized PWM Mode............................... 165 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1)....................................................... 166 Block Diagram of Channels 3 and 4 in Complementary PWM Mode ................... 169 Example of Complementary PWM Mode Setting Procedure................................. 171 Complementary PWM Mode Counter Operation................................................... 173 Example of Complementary PWM Mode Operation ............................................. 175 Example of PWM Cycle Updating......................................................................... 178 Example of Data Update in Complementary PWM Mode..................................... 179 Example of Initial Output in Complementary PWM Mode (1).............................. 180 Example of Initial Output in Complementary PWM Mode (2).............................. 181 Example of Complementary PWM Mode Waveform Output (1) .......................... 183 Example of Complementary PWM Mode Waveform Output (2) .......................... 183 Example of Complementary PWM Mode Waveform Output (3) .......................... 184 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) ... 184 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) ... 185 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) ... 185 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) ... 186 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) ... 186 Example of Toggle Output Waveform Synchronized with PWM Output.............. 187 Counter Clearing Synchronized with Another Channel ......................................... 188 Example of Output Phase Switching by External Input (1) ................................... 189 Example of Output Phase Switching by External Input (2) ................................... 190 Rev.2.00 Sep. 27, 2007 Page xxiv of xxxiv REJ09B0394-0200 Figure 8.52 Figure 8.53 Figure 8.54 Figure 8.55 Figure 8.56 Figure 8.57 Figure 8.58 Figure 8.59 Figure 8.60 Figure 8.61 Figure 8.62 Figure 8.63 Figure 8.64 Figure 8.65 Figure 8.66 Figure 8.67 Figure 8.68 Figure 8.69 Figure 8.70 Figure 8.71 Figure 8.72 Figure 8.73 Figure 8.74 Figure 8.75 Figure 8.76 Figure 8.77 Figure 8.78 Figure 8.79 Figure 8.80 Figure 8.81 Figure 8.82 Figure 8.83 Figure 8.84 Figure 8.85 Figure 8.86 Figure 8.87 Figure 8.88 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)... 190 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)... 191 Count Timing in Internal Clock Operation............................................................. 195 Count Timing in External Clock Operation ........................................................... 195 Count Timing in External Clock Operation (Phase Counting Mode)..................... 196 Output Compare Output Timing (Normal Mode/PWM Mode).............................. 196 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) .......................... 197 Input Capture Input Signal Timing......................................................................... 197 Counter Clear Timing (Compare Match) ............................................................... 198 Counter Clear Timing (Input Capture) ................................................................... 198 Buffer Operation Timing (Compare Match) .......................................................... 199 Buffer Operation Timing (Input Capture) .............................................................. 199 TGI Interrupt Timing (Compare Match) ................................................................ 200 TGI Interrupt Timing (Input Capture) .................................................................... 201 TCIV Interrupt Setting Timing............................................................................... 202 TCIU Interrupt Setting Timing............................................................................... 202 Timing for Status Flag Clearing by the CPU ......................................................... 203 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. 204 Contention between TCNT Write and Clear Operations........................................ 205 Contention between TCNT Write and Increment Operations ................................ 206 Contention between TGR Write and Compare Match ........................................... 207 Contention between Buffer Register Write and Compare Match (Channel 0) ....... 208 Contention between Buffer Register Write and Compare Match (Channels 3 and 4).................................................................................................. 209 Contention between TGR Read and Input Capture ................................................ 210 Contention between TGR Write and Input Capture ............................................... 211 Contention between Buffer Register Write and Input Capture............................... 212 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection.. 213 Counter Value during Complementary PWM Mode Stop ..................................... 214 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode.............. 215 Reset Sync PWM Mode Overflow Flag ................................................................. 216 Contention between Overflow and Counter Clearing ............................................ 217 Contention between TCNT Write and Overflow.................................................... 218 Error Occurrence in Normal Mode, Recovery in Normal Mode............................ 223 Error Occurrence in Normal Mode, Recovery in PWM Mode 1............................ 224 Error Occurrence in Normal Mode, Recovery in PWM Mode 2............................ 225 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode ............... 226 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode .... 227 Rev.2.00 Sep. 27, 2007 Page xxv of xxxiv REJ09B0394-0200 Figure 8.89 Figure 8.90 Figure 8.91 Figure 8.92 Figure 8.93 Figure 8.94 Figure 8.95 Figure 8.96 Figure 8.97 Figure 8.98 Figure 8.99 Figure 8.100 Figure 8.101 Figure 8.102 Figure 8.103 Figure 8.104 Figure 8.105 Figure 8.106 Figure 8.107 Figure 8.108 Figure 8.109 Figure 8.110 Figure 8.111 Figure 8.112 Figure 8.113 Figure 8.114 Figure 8.115 Figure 8.116 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode........................................................ 228 Error Occurrence in PWM Mode 1, Recovery in Normal Mode ........................... 229 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 ........................... 230 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 ........................... 231 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode............... 232 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode.... 233 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode........................................................ 234 Error Occurrence in PWM Mode 2, Recovery in Normal Mode ........................... 235 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 ........................... 236 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 ........................... 237 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode............... 238 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode............... 239 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1............... 240 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2............... 241 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode ........................................................................ 242 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode.... 243 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1.... 244 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode ............................................................. 245 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode ............................................................. 246 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode........................................................ 247 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode..................................................................................... 248 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1..................................................................................... 249 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode ............................................................. 250 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode........................................................ 251 POE Block Diagram............................................................................................... 253 Low-Level Detection Operation............................................................................. 259 Output-Level Detection Operation ......................................................................... 260 Falling Edge Detection Operation.......................................................................... 261 Section 9 Watchdog Timer Figure 9.1 Block Diagram of WDT......................................................................................... 264 Rev.2.00 Sep. 27, 2007 Page xxvi of xxxiv REJ09B0394-0200 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Operation in Watchdog Timer Mode ..................................................................... 270 Operation in Interval Timer Mode ......................................................................... 271 Timing of Setting OVF........................................................................................... 272 Timing of Setting WOVF....................................................................................... 272 Writing to TCNT and TCSR .................................................................................. 273 Writing to RSTCSR ............................................................................................... 274 Contention between TCNT Write and Increment................................................... 275 Example of System Reset Circuit Using WDTOVF Signal ................................... 276 Section 10 Serial Communication Interface (SCI) Figure 10.1 Block Diagram of SCI............................................................................................ 278 Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 296 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 298 Figure 10.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)............................................................................................ 299 Figure 10.5 Sample SCI Initialization Flowchart ...................................................................... 300 Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 301 Figure 10.7 Sample Serial Transmission Flowchart .................................................................. 302 Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 303 Figure 10.9 Sample Serial Reception Data Flowchart (1) ......................................................... 305 Figure 10.9 Sample Serial Reception Data Flowchart (2) ......................................................... 306 Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ........................................... 308 Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart ......................................... 309 Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................... 310 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 311 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 312 Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) ............... 313 Figure 10.15 Sample SCI Initialization Flowchart ...................................................................... 314 Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ................... 316 Figure 10.17 Sample Serial Transmission Flowchart .................................................................. 317 Figure 10.18 Example of SCI Operation in Reception ................................................................ 318 Figure 10.19 Sample Serial Reception Flowchart ....................................................................... 319 Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ....... 321 Section 11 A/D Converter Figure 11.1 Block Diagram of A/D Converter (For One Module) ............................................ 326 Rev.2.00 Sep. 27, 2007 Page xxvii of xxxiv REJ09B0394-0200 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Operation Example in Continuous Scan Mode (Three Channels Selected) (AN8 to AN10) ........................................................... 334 A/D Conversion Timing......................................................................................... 336 External Trigger Input Timing ............................................................................... 337 Definitions of A/D Conversion Accuracy .............................................................. 339 Definitions of A/D Conversion Accuracy .............................................................. 339 Example of Analog Input Circuit ........................................................................... 340 Example of Analog Input Protection Circuit.......................................................... 342 Analog Input Pin Equivalent Circuit ...................................................................... 342 Section 12 Compare Match Timer (CMT) Figure 12.1 CMT Block Diagram.............................................................................................. 343 Figure 12.2 Counter Operation.................................................................................................. 346 Figure 12.3 Count Timing ......................................................................................................... 347 Figure 12.4 CMF Set Timing .................................................................................................... 348 Figure 12.5 Timing of CMF Clear by CPU ............................................................................... 348 Figure 12.6 CMCNT Write and Compare Match Contention ................................................... 349 Figure 12.7 CMCNT Word Write and Increment Contention ................................................... 350 Figure 12.8 CMCNT Byte Write and Increment Contention..................................................... 351 Section 14 I/O Ports Figure 14.1 Port A ..................................................................................................................... 371 Figure 14.2 Port B ..................................................................................................................... 374 Figure 14.3 Port E...................................................................................................................... 376 Figure 14.4 Port F...................................................................................................................... 379 Figure 14.5 Port G ..................................................................................................................... 381 Section 15 Mask ROM Figure 15.1 Mask ROM Block Diagram ................................................................................... 383 Section 17 Power-Down Modes Figure 17.1 Mode Transition Diagram ...................................................................................... 389 Figure 17.2 NMI Timing in Software Standby Mode................................................................ 398 Section 19 Electrical Characteristics Figure 19.1 Output Load Circuit ............................................................................................... 425 Figure 19.2 System Clock Timing............................................................................................. 427 Figure 19.3 EXTAL Clock Input Timing .................................................................................. 427 Figure 19.4 Oscillation Settling Time ....................................................................................... 427 Figure 19.5 Reset Input Timing................................................................................................. 429 Figure 19.6 Reset Input Timing................................................................................................. 429 Figure 19.7 Interrupt Signal Input Timing................................................................................. 430 Figure 19.8 Interrupt Signal Output Timing.............................................................................. 430 Rev.2.00 Sep. 27, 2007 Page xxviii of xxxiv REJ09B0394-0200 Figure 19.9 Figure 19.10 Figure 19.11 Figure 19.12 Figure 19.13 Figure 19.14 Figure 19.15 Figure 19.16 MTU Input/Output Timing..................................................................................... 431 MTU Clock Input Timing ...................................................................................... 432 I/O Port Input/Output Timing................................................................................. 433 WDT Timing .......................................................................................................... 433 Input Clock Timing ................................................................................................ 434 SCI Input/Output Timing ....................................................................................... 435 POE Input/Output Timing ...................................................................................... 436 External Trigger Input Timing ............................................................................... 437 Appendix C Package Dimensions Figure C.1 FP-80Q ................................................................................................................... 443 Rev.2.00 Sep. 27, 2007 Page xxix of xxxiv REJ09B0394-0200 Rev.2.00 Sep. 27, 2007 Page xxx of xxxiv REJ09B0394-0200 Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................... 5 Table 1.2 Differences from SH7046 Group ................................................................................. 9 Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 CPU Initial Values of Registers.......................................................................................... 15 Sign Extension of Word Data .................................................................................... 17 Delayed Branch Instructions...................................................................................... 17 T Bit ........................................................................................................................... 18 Immediate Data Accessing......................................................................................... 18 Absolute Address Accessing...................................................................................... 19 Displacement Accessing ............................................................................................ 19 Addressing Modes and Effective Addresses.............................................................. 20 Instruction Formats .................................................................................................... 24 Classification of Instructions ..................................................................................... 27 Symbols Used in Instruction Code, Operation, and Execution States Tables ............ 30 Data Transfer Instructions.......................................................................................... 31 Arithmetic Operation Instructions ............................................................................. 33 Logic Operation Instructions ..................................................................................... 36 Shift Instructions........................................................................................................ 37 Branch Instructions .................................................................................................... 38 System Control Instructions....................................................................................... 39 Section 3 MCU Operating Modes Table 3.1 Selection of Operating Modes.................................................................................... 43 Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode .................................. 43 Table 3.3 Operating Mode Pin Configuration............................................................................ 44 Section 4 Clock Pulse Generator Table 4.1 Damping Resistance Values....................................................................................... 48 Table 4.2 Crystal Resonator Characteristics .............................................................................. 48 Section 5 Exception Processing Table 5.1 Types of Exception Processing and Priority .............................................................. 53 Table 5.2 Timing for Exception Source Detection and Start of Exception Processing.............. 54 Table 5.3 Exception Processing Vector Table ........................................................................... 55 Table 5.4 Calculating Exception Processing Vector Table Addresses....................................... 56 Table 5.5 Reset Status................................................................................................................ 57 Table 5.6 Bus Cycles and Address Errors.................................................................................. 59 Table 5.7 Interrupt Sources........................................................................................................ 60 Rev.2.00 Sep. 27, 2007 Page xxxi of xxxiv REJ09B0394-0200 Table 5.8 Interrupt Priority ........................................................................................................ 61 Table 5.9 Types of Exceptions Triggered by Instructions ......................................................... 62 Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction or Interrupt-Disabled Instruction ............................................................................... 64 Table 5.11 Stack Status after Exception Processing Ends ........................................................... 65 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration....................................................................................................... 68 Table 6.2 Interrupt Exception Processing Vectors and Priorities .............................................. 78 Table 6.3 Interrupt Response Time............................................................................................ 84 Section 7 Bus State Controller (BSC) Table 7.1 Address Map .............................................................................................................. 88 Table 7.2 On-chip Peripheral I/O Register Access .................................................................... 90 Section 8 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Table 8.19 Table 8.20 Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 8.25 Table 8.26 Multi-Function Timer Pulse Unit (MTU) MTU Functions.......................................................................................................... 92 Pin configuration........................................................................................................ 95 CCLR0 to CCLR2 (channels 0, 3, and 4) .................................................................. 99 CCLR0 to CCLR2 (channels 1 and 2) ....................................................................... 99 TPSC0 to TPSC2 (channel 0) .................................................................................. 100 TPSC0 to TPSC2 (channel 1) .................................................................................. 100 TPSC0 to TPSC2 (channel 2) .................................................................................. 101 TPSC0 to TPSC2 (channels 3 and 4) ....................................................................... 101 MD0 to MD3 ........................................................................................................... 103 TIORH_0 (channel 0) .............................................................................................. 106 TIORH_0 (channel 0) .............................................................................................. 107 TIORL_0 (channel 0)............................................................................................... 108 TIORL_0 (channel 0)............................................................................................... 109 TIOR_1 (channel 1) ................................................................................................. 110 TIOR_1 (channel 1) ................................................................................................. 111 TIOR_2 (channel 2) ................................................................................................. 112 TIOR_2 (channel 2) ................................................................................................. 113 TIORH_3 (channel 3) .............................................................................................. 114 TIORH_3 (channel 3) .............................................................................................. 115 TIORL_3 (channel 3)............................................................................................... 116 TIORL_3 (channel 3)............................................................................................... 117 TIORH_4 (channel 4) .............................................................................................. 118 TIORH_4 (channel 4) .............................................................................................. 119 TIORL_4 (channel 4)............................................................................................... 120 TIORL_4 (channel 4)............................................................................................... 121 Output Level Select Function .................................................................................. 131 Rev.2.00 Sep. 27, 2007 Page xxxii of xxxiv REJ09B0394-0200 Table 8.27 Table 8.28 Table 8.29 Table 8.30 Table 8.31 Table 8.32 Table 8.33 Table 8.34 Table 8.35 Table 8.36 Table 8.37 Table 8.38 Table 8.39 Table 8.40 Table 8.41 Table 8.42 Table 8.43 Table 8.44 Table 8.45 Output Level Select Function .................................................................................. 132 Output level Select Function.................................................................................... 134 Register Combinations in Buffer Operation ............................................................ 145 Cascaded Combinations........................................................................................... 149 PWM Output Registers and Output Pins ................................................................. 151 Phase Counting Mode Clock Input Pins .................................................................. 156 Up/Down-Count Conditions in Phase Counting Mode 1......................................... 158 Up/Down-Count Conditions in Phase Counting Mode 2......................................... 159 Up/Down-Count Conditions in Phase Counting Mode 3......................................... 160 Up/Down-Count Conditions in Phase Counting Mode 4......................................... 161 Output Pins for Reset-Synchronized PWM Mode ................................................... 163 Register Settings for Reset-Synchronized PWM Mode ........................................... 163 Output Pins for Complementary PWM Mode.......................................................... 167 Register Settings for Complementary PWM Mode ................................................. 168 Registers and Counters Requiring Initialization ...................................................... 176 MTU Interrupts ........................................................................................................ 193 Mode Transition Combinations ............................................................................... 221 Pin Configuration..................................................................................................... 254 Pin Combinations..................................................................................................... 254 Section 9 Watchdog Timer Table 9.1 Pin Configuration..................................................................................................... 264 Table 9.2 WDT Interrupt Source (in Interval Timer Mode) .................................................... 273 Section 10 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Section 11 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Serial Communication Interface (SCI) Pin Configuration..................................................................................................... 279 Relationships between N Setting in BRR and Effective Bit Rate B0 ....................... 288 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................... 289 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode) ............................................................................................. 291 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................... 292 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ........................ 293 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ....... 295 Serial Transfer Formats (Asynchronous Mode)....................................................... 297 SSR Status Flags and Receive Data Handling ......................................................... 304 SCI Interrupt Sources............................................................................................... 322 A/D Converter Pin Configuration..................................................................................................... 327 Channel Select List .................................................................................................. 330 A/D Conversion Time (Single Mode)...................................................................... 336 A/D Conversion Time (Scan Mode) ........................................................................ 337 Rev.2.00 Sep. 27, 2007 Page xxxiii of xxxiv REJ09B0394-0200 Table 11.5 A/D Converter Interrupt Source............................................................................... 338 Table 11.6 Analog Pin Specifications........................................................................................ 342 Section 13 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Pin Function Controller (PFC) Multiplexed Pins (Port A)........................................................................................ 353 Multiplexed Pins (Port B) ........................................................................................ 354 Multiplexed Pins (Port E) ........................................................................................ 355 Multiplexed Pins (Port F)......................................................................................... 356 Multiplexed Pins (Port G)........................................................................................ 356 Pin Functions in Each Operating Mode ................................................................... 357 I/O Ports Port A Data Register L (PADRL) Read/Write Operations ...................................... 373 Port B Data Register (PBDR) Read/Write Operations............................................. 375 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations ...... 378 Port F Data Register (PFDR) Read/Write Operations ............................................. 380 Port G Data Register (PGDR) Read/Write Operations ............................................ 382 Section 17 Power-Down Modes Table 17.1 Internal Operation States in Each Mode .................................................................. 388 Table 17.2 Pin Configuration..................................................................................................... 389 Section 19 Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Table 19.9 Table 19.10 Table 19.11 Table 19.12 Electrical Characteristics Absolute Maximum Ratings .................................................................................... 421 DC Characteristics ................................................................................................... 422 Permitted Output Current Values............................................................................. 424 Clock Timing ........................................................................................................... 426 Control Signal Timing ............................................................................................. 428 Multi-Function Timer Pulse Unit Timing ................................................................ 431 I/O Port Timing........................................................................................................ 432 Watchdog Timer Timing.......................................................................................... 433 Serial Communication Interface Timing.................................................................. 434 Output Enable Timing ............................................................................................. 436 A/D Converter Timing............................................................................................. 436 A/D Converter Characteristics ................................................................................. 438 Appendix A Pin States Table A.1 Pin States ................................................................................................................. 439 Rev.2.00 Sep. 27, 2007 Page xxxiv of xxxiv REJ09B0394-0200 1. Overview Section 1 Overview The SH7101 single-chip RISC (Reduced Instruction Set Computer) microcomputer integrates a Renesas Technology-original RISC CPU core with peripheral functions required for system configuration. The SH7101 CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds. In addition, the SH7101 includes on-chip peripheral functions necessary for system configuration, such as ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. As the on-chip ROM, only mask ROM version is available. However, when F-ZTAT (Flexible Zero Turn Around Time) version is required, the SH7046F can be used. TM 1.1 Features * Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: multiplication operations (32 bits x 32 bits 64 bits) executed in two to four cycles C language-oriented 62 basic instructions * Various peripheral functions Multifunction timer/pulse unit (MTU) Compare match timer (CMT) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) 10-bit A/D converter Clock pulse generator Rev.2.00 Sep. 27, 2007 Page 1 of 448 REJ09B0394-0200 1. Overview * On-chip memory ROM Mask ROM Version Model HD6437101 ROM 32 kbytes RAM 2 kbytes Remarks * Maximum operating frequency and operating temperature range Model HD6437101F40 Maximum operating frequency (MHz) (system clock () and peripheral clock (P)) (40, 40) Operating temperature range (C) -20 to +75 -40 to +85 HD6437101FW40 (40, 40) * I/O ports Model HD6437101 No. of I/O Pins 42 No. of Input-only Pins 12 * Supports various power-down states * Compact package Model HD6437101 Package QFP-80 Package (Code) FP-80Q Body Size 14.0 Pin Pitch 0.65 mm x 14.0 mm Rev.2.00 Sep. 27, 2007 Page 2 of 448 REJ09B0394-0200 1. Overview 1.2 Internal Block Diagram PA11/ADTRG/SCK3 PA8/TCLKC/RxD3 PA6/TCLKA/RxD2 PA9/TCLKD/TxD3 PA7/TCLKB/TxD2 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PB3/IRQ1/POE1 PA0/POE0/RxD2 PA1/POE1/TxD2 PA5/IRQ1/SCK3 PA2/IRQ0/SCK2 PB2/IRQ0/POE0 PA10/SCK2 RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcL PLLCAP PLLVss FWP VcL VcL Vcc Vcc Vcc Vss Vss Vss Vss AVcc AVcc AVss AVss Compare match timer (x2 channels) A/D Watchdog converter timer Serial communication interface (x2 channels) Multifunction timer pulse unit Interrupt controller Bus state controller CPU Mask ROM 32 kbytes RAM 2 kbytes PLL PG3 PG2 PG1 PG0 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PE21 PE20 PE19 PE18 PE17 PE16 PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D PE10/TIOC3C PE9/TIOC3B PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A/SCK3 PE5/TIOC1B/TxD3 PE4/TIOC1A/RxD3 PE3/TIOC0D PE2/TIOC0C PE1/TIOC0B PE0/TIOC0A PA3/RxD3 PA4/TxD3 PA12 PA15 PA14 PA13 : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Figure 1.1 Internal Block Diagram of SH7101 Rev.2.00 Sep. 27, 2007 Page 3 of 448 REJ09B0394-0200 1.3 1. Overview Pin Arrangement PA1/POE1/TXD2 VcL PA0/POE0/RXD2 Vss FWP Vcc RES NMI MD3 MD2 MD1 MD0 EXTAL XTAL PLLVcL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Rev.2.00 Sep. 27, 2007 Page 4 of 448 REJ09B0394-0200 Note: * This pin has a pull-up MOS. QFP-80 (Top view) Figure 1.2 SH7101 Pin Arrangement PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RXD3 PE5/TIOC1B/TXD3 PE6/TIOC2A/SCK3 PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B Vss PE10/TIOC3C Vcc PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT *PE16 *PE17 *PE18 *PE19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PA2/IRQ0/SCK2 PA3/RxD3 PA4/TxD3 PA5/IRQ1/SCK3 PA6/TCLKA/RxD2 PA7/TCLKB/TxD2 PA8/TCLKC/RxD3 PA9/TCLKD/TxD3 PA10/SCK2 PA11/ADTRG/SCK3 PA12* PA13* PA14* PA15* PB2/IRQ0/POE0 PB3/IRQ1/POE1 PB4/IRQ2/POE2 Vcc PB5/IRQ3/POE3 Vss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AVss PF8/AN8 AVcc PF9/AN9 PF10/AN10 PF11/AN11 PG0 PG1 PG2 PG3 PF12/AN12 PF13/AN13 PF14/AN14 AVcc PF15/AN15 AVss Vss PE21* VcL PE20* 1. Overview 1.4 Table 1.1 Type Power Supply Pin Functions Pin Functions Symbol VCC I/O Input Name Power supply Function Power supply pins. Connect all these pins to the system power supply. The chip does not operate normally when some of these pins are open. Ground pins. Connect all these pins to the system power supply (0 V). The chip does not operate normally when some of these pins are open. External capacitance pins for internal power-down power supply. Connect these pins to VSS via a 0.47 F (-10%/+100%) capacitor (placed close to the pins). External capacitance pin for internal power-down power supply for an on-chip PLL oscillator. Connect this pin to PLLVSS via a 0.47 F (-10%/+100%) capacitor (placed close to the pin). On-chip PLL oscillator ground pin. External capacitance pin for an on-chip PLL oscillator. VSS Input Ground VCL Output Power supply for internal power-down Power supply for PLL Clock PLLVCL Output PLLVSS PLLCAP EXTAL Input Input Input Ground for PLL Capacitance for PLL External clock For connection to a crystal resonator. (An external clock can be supplied from the EXTAL pin.) For examples of crystal resonator connection and external clock input, see section 4, Clock Pulse Generator. Crystal For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 4, Clock Pulse Generator. Set the operating mode. Inputs at these pins should not be changed during operation. XTAL Input Operating MD3 to MD0 mode control Input Set the mode Rev.2.00 Sep. 27, 2007 Page 5 of 448 REJ09B0394-0200 1. Overview Type Symbol I/O Input Name Protection against write operation into Flash memory Power on reset Manual reset Function Pin for the flash memory. This pin is only used in the flash memory version. Writing or erasing of flash memory can be protected. This pin becomes the Vcc pin for the mask ROM version. When this pin is driven low, the chip becomes to power on reset state. When this pin is driven low, the chip becomes to manual reset state. Operating FWP mode control System control RES MRES WDTOVF Input Input Output Watchdog Output signal for the watchdog timer timer overflow overflow. This pin should be pulled down with at least 1 M resistor value. Non-maskable Non-maskable interrupt pin. If this pin is interrupt not used, it should be fixed high or low. Interrupt request 3 to 0 These pins request a maskable interrupt. One of the level input or edge input can be selected. In case of the edge input, one of the rising edge, falling edge, or both can be selected. Interrupts NMI Input IRQ3 to IRQ0 Input IRQOUT Multi function TCLKA timer-pulse TCLKB unit (MTU) TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B Output Input Interrupt Shows that an interrupt cause has request output occurred. External clock These pins input an external clock. input for MTU timer MTU input The TGRA_0 to TGRD_0 input capture capture/output input/output compare output/PWM output compare pins. (channel 0) MTU input The TGRA_1 to TGRB_1 input capture capture/output input/output compare output/PWM output compare pins. (channel 1) MTU input The TGRA_2 to TGRB_2 input capture capture/output input/output compare output/PWM output compare pins. (channel 2) Input/ Output Input/ Output TIOC2A TIOC2B Input/ Output Rev.2.00 Sep. 27, 2007 Page 6 of 448 REJ09B0394-0200 1. Overview Type Symbol I/O Input/ Output Name Function Multi function TIOC3A TIOC3B timer-pulse TIOC3C unit (MTU) TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Serial communication Interface (SCI) TxD2 TxD3 RxD2 RxD3 SCK2 SCK3 MTU output control A/D converter POE3 to POE0 The TGRA_3 to TGRD_3 input capture MTU input capture/output input/output compare output/PWM output pins. compare (channel 3) MTU input The TGRA_4 to TGRB_4 input capture capture/output input/output compare output/PWM output compare pins. (channel 4) Transmitted data Data output pins. Input/ Output Output Input Input/ Output Input Received data Data input pins. Serial clock Port output control Analog input pins Clock input/output pins. Input pins for the signal to request the output pins of MTU waveform to become high impedance state. Analog input pins. 8 channels: AN15 to AN8 AN15 to AN8 Input ADTRG Input Input of trigger Pin for input of an external trigger to start for A/D A/D conversion conversion Analog power supply Power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Connect all AVCC pins to the power supply. The chip does not operate normally when some of these pins are open. AVCC Input AVSS Input Analog ground The ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Connect all AVSS pins to the system power supply. The chip does not operate normally when some of these pins are open. Rev.2.00 Sep. 27, 2007 Page 7 of 448 REJ09B0394-0200 1. Overview Type I/O ports Symbol I/O Name General purpose port General purpose port General purpose port General purpose port General purpose port Function 16-bit general purpose input/output port pins. PA15 to PA12 have a pull-up MOS. 4-bit general purpose input/output port pins 22-bit general purpose input/output port pins. PE21 to PE16 have a pull-up MOS. 8-bit general purpose input port pins 4-bit general purpose input port pins PA15 to PA0 Input/ Output PB5 to PB2 Input/ Output PE21 to PE0 Input/ Output PF15 to PF8 PG3 to PG0 Input Input Rev.2.00 Sep. 27, 2007 Page 8 of 448 REJ09B0394-0200 1. Overview 1.5 Table 1.2 Item Differences from SH7046 Group Differences from SH7046 Group SH7046F Incorporated Registers IPRA and IPRD to IPRK available. Registers BCR1, BCR2, WCR1, and RAMER POE6 to POE0 4ch x 3 modules AN19 to AN8 PA2/IRQ0/PCIO/SCK2 PA3/POE4/RXD3 PA4/POE5/TXD3 PA5/IRQ1/POE6/SCK3 PA8/TCLKC/IRQ2/RXD3 PA9/TCLKD/IRQ3/TXD3 PA12/UBCTRG PA13/POE4 PA14/POE5 PA15/POE6 PE7/TIOC2B/RXD2 PE8/TIOC3A/SCK2 PE10/TIOC3C/TXD2 PE16/PUOA/UBCTRG PE17/PVOA PE18/PWOA SH7101 Not incorporated Registers IPRJ and IPRK deleted. Registers BCR2, WCR1, and RAMER deleted. POE6 to POE4 for MMT deleted. 4ch x 2 modules AN15 to AN8 PA2/IRQ0/SCK2 PA3/RXD3 PA4/TXD3 PA5/IRQ1/SCK3 PA8/TCLKC/RXD3 PA9/TCLKD/TXD3 PA12 (pulled up when used as general purpose input) PA13 (pulled up when used as general purpose input) PA14 (pulled up when used as general purpose input) PA15 (pulled up when used as general purpose input) PE7/TIOC2B PE8/TIOC3A PE10/TIOC3C PE16 (pulled up when used as general purpose input)* PE17 (pulled up when used as general purpose input)* PE18 (pulled up when used as general purpose input)* DTC, MMT, UBC INT BSC POE A/D Converter I/O port PFC Rev.2.00 Sep. 27, 2007 Page 9 of 448 REJ09B0394-0200 1. Overview Item I/O port PFC PE20/PVOB PE21/PWOB PG0/AN16 PG1/AN17 PG2/AN18 PG3/AN19 ROM RAM Operating clock Note: * Flash 256 kbytes 12 kbytes 4 to 50 MHz SH7046F PE19/PUOB SH7101 PE19 (pulled up when used as general purpose input)* PE20 (pulled up when used as general purpose input)* PE21 (pulled up when used as general purpose input)* PG0 PG1 PG2 PG3 Mask ROM 32 kbytes 2 kbytes 10 to 40 MHz Pins PE21 to PE16 also functioned as high-current function pins. Howwever, in the SH7101, pins PE21 to PE16 are exclusively for general input/output. Rev.2.00 Sep. 27, 2007 Page 10 of 448 REJ09B0394-0200 2. CPU Section 2 CPU 2.1 Features * General-register architecture Sixteen 32-bit general registers * Sixty-two basic instructions * Eleven addressing modes Register direct [Rn] Register indirect [@Rn] Register indirect with post-increment [@Rn+] Register indirect with pre-decrement [@-Rn] Register indirect with displacement [@disp:4,Rn] Register indirect with index [@R0, Rn] GBR indirect with displacement [@disp:8,GBR] GBR indirect with index [@R0,GBR] Program-counter relative with displacement [@disp:8,PC] Program-counter relative [disp:8/disp:12/Rn] Immediate [#imm:8] 2.2 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. CPUS200A_010020030200 Rev.2.00 Sep. 27, 2007 Page 11 of 448 REJ09B0394-0200 2. CPU General registers (Rn) 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0 Status register (SR) 31 9 8765 43 210 M Q I3 I2 I1 I0 ST Global base register (GBR) 31 GBR 0 Vector base register (VBR) 31 VBR 0 Multiply-accumulate register (MAC) 31 MACH MACL 0 Procedure register (PR) 31 PR 0 Program counter (PC) 31 PC 0 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 CPU Internal Registers Rev.2.00 Sep. 27, 2007 Page 12 of 448 REJ09B0394-0200 2. CPU 2.2.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. 2.2.2 Control Registers The control registers consist of three 32-bit registers: status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Status Register (SR): Initial Value All 0 Bit Bit Name R/W R/W Description Reserved This bit is always read as 0. The write value should always be 0. 31 to 10 9 8 7 6 5 4 3, 2 M Q I3 I2 I1 I0 Undefined R/W Undefined R/W 1 1 1 1 All 0 R/W R/W R/W R/W R/W Used by the DIV0U, DIV0S, and DIV1 instructions. Used by the DIV0U, DIV0S, and DIV1 instructions. Interrupt mask bits. Reserved This bit is always read as 0. The write value should always be 0. 1 S Undefined R/W S bit Used by the MAC instruction. Rev.2.00 Sep. 27, 2007 Page 13 of 448 REJ09B0394-0200 2. CPU Initial Value Bit 0 Bit Name T R/W Description T bit The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. Undefined R/W Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. Vector Base Register (VBR): Indicates the base address of the exception processing vector area. 2.2.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-andaccumulate operations. Procedure Register (PR): Registers to store the return address from a subroutine procedure. Program Counter (PC): Registers to indicate the sum of current instruction addresses and four, that is, the address of the second instruction after the current instruction. Rev.2.00 Sep. 27, 2007 Page 14 of 448 REJ09B0394-0200 2. CPU 2.2.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I3 to I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Classification General registers 2.3 2.3.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 Longword 0 Figure 2.2 Data Format in Registers Rev.2.00 Sep. 27, 2007 Page 15 of 448 REJ09B0394-0200 2. CPU 2.3.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword 23 Byte Address m + 3 Address m + 2 15 Byte Word 7 Byte 0 Figure 2.3 Data Formats in Memory 2.3.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Rev.2.00 Sep. 27, 2007 Page 16 of 448 REJ09B0394-0200 2. CPU 2.4 2.4.1 Instruction Features RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per State: The microprocessor can execute basic instructions in one state using the pipeline system. One state is 25 ns at 40 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data. Table 2.2 Sign Extension of Word Data Description Example of Conventional CPU ADD.W #H'1234,R0 CPU of This LSI MOV.W ADD .DATA.W @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD H'1234 instruction. Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. This reduces the disturbance of the pipeline control in case of branch instructions. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Table 2.3 Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Conventional CPU ADD.W BRA R1,R0 TRGET CPU of This LSI BRA ADD TRGET R1,R0 Rev.2.00 Sep. 27, 2007 Page 17 of 448 REJ09B0394-0200 2. CPU Multiply/Multiply-and-Accumulate Operations: 16-bit x 16-bit 32-bit multiply operations are executed in one to two states. 16-bit x 16-bit + 64-bit 4-bit multiply-and-accumulate operations are executed in two to three states. 32-bit x 32-bit 64-bit multiply and 32-bit x 32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four states. T Bit: The T bit in the status register changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Table 2.4 T Bit Description T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. Example of Conventional CPU CMP.W BGE BLT R1,R0 TRGET0 TRGET1 #1,R0 TRGET CPU of This LSI CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET T bit is not changed by ADD. T bit is SUB.W set when R0 = 0. The program BEQ branches if R0 = 0. Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Table 2.5 Immediate Data Accessing CPU of This LSI MOV MOV.W .DATA.W 32-bit immediate MOV.L .DATA.L #H'12,R0 @(disp,PC),R0 ................. H'1234 @(disp,PC),R0 ................. H'12345678 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 Classification 8-bit immediate 16-bit immediate MOV.L #H'12345678,R0 Note: @(disp, PC) accesses the immediate data. Rev.2.00 Sep. 27, 2007 Page 18 of 448 REJ09B0394-0200 2. CPU Absolute Address: When data is accessed by absolute address, the value in the absolute address is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect register addressing mode. Table 2.6 Absolute Address Accessing CPU of This LSI MOV.L MOV.B .DATA.L @(disp,PC),R1 @R1,R0 .................. H'12345678 Note: @(disp, PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0 Classification Absolute address 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the displacement value is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect indexed register addressing mode. Table 2.7 Displacement Accessing CPU of This LSI MOV.W MOV.W .DATA.W @(disp,PC),R0 @(R0,R1),R2 .................. H'1234 Note: @(disp, PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement Rev.2.00 Sep. 27, 2007 Page 19 of 448 REJ09B0394-0200 2. CPU 2.4.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Mode Direct register addressing Indirect register addressing Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Rn @Rn Equation The effective address is register Rn. (The operand is the contents of register Rn.) The effective address is the contents of register Rn. Rn Rn Rn Post-increment indirect register addressing @Rn+ The effective address is the contents of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn Rn (After the instruction executes) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction is executed with Rn after this calculation) Pre-decrement indirect register addressing @-Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4 Rev.2.00 Sep. 27, 2007 Page 20 of 448 REJ09B0394-0200 2. CPU Addressing Mode Indirect register addressing with displacement Instruction Format Effective Address Calculation @(disp:4, The effective address is the sum of Rn and a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Equation Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 Indirect indexed register addressing @(R0, Rn) The effective address is the sum of Rn and R0. Rn + R0 Rn + R0 Rn + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the sum of GBR value and GBR) an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 Indirect indexed @(R0, GBR addressing GBR) The effective address is the sum of GBR value and GBR + R0 R0. GBR + R0 GBR + R0 Rev.2.00 Sep. 27, 2007 Page 21 of 448 REJ09B0394-0200 2. CPU Addressing Mode Indirect PC addressing with displacement Instruction Format Effective Address Calculation @(disp:8, The effective address is the sum of PC value and PC) an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) x 2/4 (for longword) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 Equation Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4 + PC relative addressing disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). PC disp (sign-extended) x 2 + PC + disp x 2 PC + disp x 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC disp (sign-extended) x 2 + PC + disp x 2 PC + disp x 2 Rev.2.00 Sep. 27, 2007 Page 22 of 448 REJ09B0394-0200 2. CPU Addressing Mode PC relative addressing Instruction Format Effective Address Calculation Rn Equation The effective address is the sum of the register PC PC + Rn and Rn. PC + Rn PC + Rn Immediate addressing #imm:8 #imm:8 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. Rev.2.00 Sep. 27, 2007 Page 23 of 448 REJ09B0394-0200 2. CPU 2.4.3 Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: * xxxx: Instruction code * mmmm: Source register * nnnn: Destination register * iiii: Immediate data * dddd: Displacement Table 2.9 Instruction Formats Source Operand 0 xxxx xxxx xxxx xxxx Instruction Formats 0 format 15 Destination Operand Example NOP n format 15 xxxx nnnn xxxx xxxx 0 Control register or system register Control register or system register nnnn: Direct register nnnn: Direct register nnnn: Indirect predecrement register Control register or system register Control register or system register MOVT STS Rn MACH,Rn STC.L SR,@-Rn LDC Rm,SR m format 15 xxxx mmmm xxxx xxxx 0 mmmm: Direct register mmmm: Indirect post-increment register mmmm: Indirect register mmmm: PC relative using Rm LDC.L @Rm+,SR JMP BRAF @Rm Rm Rev.2.00 Sep. 27, 2007 Page 24 of 448 REJ09B0394-0200 2. CPU Source Operand 0 xxxx nnnn mmmm xxxx Instruction Formats nm format 15 Destination Operand nnnn: Direct register nnnn: Indirect register MACH, MACL Example ADD Rm,Rn mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiplyand-accumulate) nnnn*: Indirect post-increment register (multiplyand-accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rn),R0 md format 15 xxxx xxxx mmmm dddd 0 mmmmdddd: Indirect register with displacement nd4 format 15 xxxx xxxx nnnn dddd 0 R0 (Direct register) nnnndddd: Indirect register with displacement mmmm: Direct register mmmmdddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register MOV.B R0,@(disp,Rn) nmd format 15 xxxx nnnn mmmm dddd 0 MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Rev.2.00 Sep. 27, 2007 Page 25 of 448 REJ09B0394-0200 2. CPU Source Operand 0 xxxx xxxx dddd dddd Instruction Formats d format 15 Destination Operand R0 (Direct register) Example MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR) MOVA @(disp,PC),R0 BF BRA label label dddddddd: Indirect GBR with displacement R0 (Direct register) dddddddd: Indirect GBR with displacement dddddddd: PC relative with displacement d12 format 15 xxxx dddd dddd dddd 0 R0 (Direct register) dddddddd: PC relative dddddddddddd: PC relative (label = disp + PC) MOV.L @(disp,PC),Rn nd8 format 15 xxxx nnnn dddd dddd 0 dddddddd: PC relative with displacement iiiiiiii: Immediate nnnn: Direct register i format 15 xxxx xxxx iiii iiii 0 Indirect indexed GBR R0 (Direct register) nnnn: Direct register AND.B #imm,@(R0,GBR) AND TRAPA ADD #imm,R0 #imm #imm,Rn iiiiiiii: Immediate iiiiiiii: Immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. 2.5 2.5.1 Instruction Set Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Rev.2.00 Sep. 27, 2007 Page 26 of 448 REJ09B0394-0200 2. CPU Table 2.10 Classification of Instructions Operation Classification Types Code Function Data transfer 5 MOV Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check 33 No. of Instructions 39 MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-length multiply-and-accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Rev.2.00 Sep. 27, 2007 Page 27 of 448 REJ09B0394-0200 2. CPU Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 11 14 No. of Instructions 14 Rev.2.00 Sep. 27, 2007 Page 28 of 448 REJ09B0394-0200 2. CPU Operation Classification Types Code Function System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Transition to power-down mode Store control register data Store system register data Trap exception handling 142 No. of Instructions 31 The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Rev.2.00 Sep. 27, 2007 Page 29 of 448 REJ09B0394-0200 2. CPU Table 2.11 Symbols Used in Instruction Code, Operation, and Execution States Tables Item Instruction Format Described in mnemonic. OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement*2 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted*1 Value of T bit after instruction is executed. An em-dash () in the column means no change. Instruction code Described in MSB LSB order Outline of the Operation , (xx) M/Q/T & | ^ ~ < Execution states T bit Notes: 1. Instruction execution states: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by x1, x2, or x4. For details, refer the SH-1/SH-2/SH-DSP Software Manual. Rev.2.00 Sep. 27, 2007 Page 30 of 448 REJ09B0394-0200 2. CPU Data Transfer Instructions Table 2.12 Data Transfer Instructions Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd Operation #imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn, Rm + 1 Rm (Rm) Sign extension Rn, Rm + 2 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (Rm) Rn, Rm + 4 Rm 1 1 1 1 1 1 Rev.2.00 Sep. 27, 2007 Page 31 of 448 REJ09B0394-0200 2. CPU Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 Operation (disp x 4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) Sign extension R0 (disp x 2 + GBR) Sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC R0 T Rn Rm Swap bottom two bytes Rn Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn T Bit R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 Rn 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev.2.00 Sep. 27, 2007 Page 32 of 448 REJ09B0394-0200 2. CPU Arithmetic Operation Instructions Table 2.13 Arithmetic Operation Instructions Execution States 1 1 1 1 1 1 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T T Bit Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result If Rn Rm with unsigned 1 data, 1 T If Rn Rm with signed data, 1 T 1 If Rn > Rm with unsigned 1 data, 1 T If Rn > Rm with signed data, 1 T If Rn > 0, 1 T If Rn 0, 1 T If Rn and Rm have an equivalent byte, 1T Single-step division (Rn / Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 1 1 1 1 CMP/STR Rm,Rn DIV1 DIV0S Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 1 1 Rev.2.00 Sep. 27, 2007 Page 33 of 448 REJ09B0394-0200 2. CPU Execution States 1 Instruction DIV0U DMULS.L Rm,Rn Instruction Code 0000000000011001 0011nnnnmmmm1101 Operation 0 M/Q/T T Bit 0 Signed operation of 2 to 4* Rn x Rm MACH, MACL 32 x 32 64 bits 2 to 4* Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, when Rn 1 is 0, 1 T. When Rn is nonzero, 0 T Byte in Rm is signextended Rn Word in Rm is signextended Rn Byte in Rm is zeroextended Rn Word in Rm is zeroextended Rn Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bits Rn x Rm MACL, 32 x 32 32 bits Signed operation of Rn x Rm MACL 16 x 16 32 bits Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 0 - Rm Rn 0 - Rm - T Rn, Borrow T 1 1 1 1 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 Comparison result EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 @Rm+,@Rn+ 0000nnnnmmmm1111 3/ (2 to 4)* MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 3/(2)* MUL.L MULS.W Rm,Rn Rm,Rn 0000nnnnmmmm0111 0010nnnnmmmm1111 2 to 4* 1 to 3* MULU.W Rm,Rn 0010nnnnmmmm1110 1 to 3* NEG NEGC Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 1 1 Borrow Rev.2.00 Sep. 27, 2007 Page 34 of 448 REJ09B0394-0200 2. CPU Execution States 1 1 1 Instruction SUB SUBC SUBV Note: * Rm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 Operation Rn - Rm Rn Rn - Rm - T Rn, Borrow T Rn - Rm Rn, Underflow T T Bit Borrow Overflow The normal number of execution states is shown. (The number in parentheses is the number of states when there is contention with the preceding or following instructions.) Rev.2.00 Sep. 27, 2007 Page 35 of 448 REJ09B0394-0200 2. CPU Logic Operation Instructions Table 2.14 Logic Operation Instructions Execution States 1 1 3 1 1 1 3 4 1 1 Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) @Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T T Bit Test result Test result Test result Test result (R0 + GBR) & imm; if the 3 result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 1 1 (R0 + GBR) ^ imm (R0 3 + GBR) Rev.2.00 Sep. 27, 2007 Page 36 of 448 REJ09B0394-0200 2. CPU Shift Instructions Table 2.15 Shift Instructions Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T Rn MSB LSB Rn T T Rn T T Rn T T Rn 0 MSB Rn T T Rn 0 0 Rn T Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn T Bit MSB LSB MSB LSB MSB LSB MSB LSB SHLL16 Rn SHLR16 Rn Rev.2.00 Sep. 27, 2007 Page 37 of 448 REJ09B0394-0200 2. CPU Branch Instructions Table 2.16 Branch Instructions Execution States 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 Instruction BF label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC T Bit BF/S label BT label BT/S label BRA label BRAF Rm BSR label BSRF Rm JMP JSR RTS Note: * @Rm @Rm One state when the program does not branch. Rev.2.00 Sep. 27, 2007 Page 38 of 448 REJ09B0394-0200 2. CPU System Control Instructions Table 2.17 System Control Instructions Execution States 1 1 1 1 1 3 3 3 1 1 1 Instruction CLRT CLRMAC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn Rm,SR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 Operation 0T 0 MACH, MACL Rm SR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm No operation Delayed branch, stack area PC/SR 1T Sleep SR Rn GBR Rn VBR Rn Rn - 4 Rn, SR (Rn) Rn - 4 Rn, GBR (Rn) Rn - 4 Rn, VBR (Rn) T Bit 0 LSB LSB 1 (Rm) MACH, Rm + 4 Rm 1 1 1 1 4 1 3* 1 1 1 2 2 2 Rev.2.00 Sep. 27, 2007 Page 39 of 448 REJ09B0394-0200 2. CPU Execution States 1 1 1 1 1 1 Instruction STS STS STS STS.L STS.L STS.L TRAPA Note: MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm * Instruction Code 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation MACH Rn MACL Rn PR Rn Rn - 4 Rn, MACH (Rn) Rn - 4 Rn, MACL (Rn) Rn - 4 Rn, PR (Rn) T Bit PC/SR stack area, (imm x 4 8 + VBR) PC The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction. Rev.2.00 Sep. 27, 2007 Page 40 of 448 REJ09B0394-0200 2. CPU 2.6 2.6.1 Processing States State Transitions The CPU has four processing states: reset, exception processing, program execution and powerdown. Figure 2.4 shows the transitions between the states. From any state when RES = 0 From any state when RES = 1 and MRES = 0 Power-on reset state RES = 0 Manual reset state RES = 1 Exception processing state When a power-on reset or manual reset occurred by WDT Exception processing source occurs RES = 1, MRES = 1 Reset state NMI or IRQ interrupt occurs Exception processing ends Program execution state SSBY bit cleared for SLEEP instruction SSBY bit set for SLEEP instruction Sleep mode Software standby mode Power-down state Figure 2.4 Transitions between Processing States Rev.2.00 Sep. 27, 2007 Page 41 of 448 REJ09B0394-0200 2. CPU Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is entered. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. Rev.2.00 Sep. 27, 2007 Page 42 of 448 REJ09B0394-0200 3. MCU Operating Modes Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has one operating mode and four clock modes. The operating mode is determined by the setting of MD3 to MD0, and FWP pins. Do not change these pins during LSI operation (while power is on). Do not set these pins in the other way than the combination shown in table 3.1. This LSI supports only mode 3. Table 3.1 Mode No. Selection of Operating Modes Pin Setting FWP MD3 x MD2 x MD1 MD0 Mode Name 1 1 Single chip mode On-Chip ROM Active Mode 3 1 Note: The symbol x means "Don't care." The clock mode is selected by the input of MD2 and MD3 pins. Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode Pin Setting MD3 0 0 1 1 Note: * MD2 0 1 0 1 Maximum Operating Clock Frequency 10 MHz (Input clock x 1, maximum of input clock: 10 MHz) 20 MHz (Input clock x 2, maximum of input clock: 10 MHz) 40 MHz (Input clock x 4*, maximum of input clock: 10 MHz) 40 MHz (Input clock x 4 for system clock, Input clock x 2 for peripheral clock, maximum of input clock: 10 MHz) The maximum of input clock is 10 MHz so that P is lower or equal to 40 MHz. Rev.2.00 Sep. 27, 2007 Page 43 of 448 REJ09B0394-0200 3. MCU Operating Modes 3.2 Input/Output Pins Table 3.3 describes the configuration of operating mode related pins. Table 3.3 Pin Name MD0 MD1 MD2 MD3 FWP Operating Mode Pin Configuration Input/Output Input Input Input Input Input Function Designates operating mode through the level applied to this pin Designates operating mode through the level applied to this pin Designates clock mode through the level applied to this pin Designates clock mode through the level applied to this pin Pin for the hardware protection against writing/erasing the on-chip flash memory. In this LSI, conncet this pin to VCC. 3.3 Explanation of Operating Modes This LSI does not support modes 0 to 2 (MCU extension mode 0 to 2). 3.3.1 Mode 3 (Single chip mode) All ports can be used in this mode, however the external address cannot be used. The SH7101 supports only this mode. 3.3.2 Clock Mode The input waveform frequency can be used as is, doubled or quadrupled as system clock frequency. Rev.2.00 Sep. 27, 2007 Page 44 of 448 REJ09B0394-0200 3. MCU Operating Modes 3.4 Address Map Figure 3.1 shows the address map. ROM: 32 kbytes, RAM: 2 kbytes Mode 3 H'00000000 On-chip ROM H'00007FFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFF800 On-chip RAM H'FFFFFFFF Figure 3.1 Address Map for SH7101 Mask ROM Version Rev.2.00 Sep. 27, 2007 Page 45 of 448 REJ09B0394-0200 3. MCU Operating Modes 3.5 Initial State of This LSI To reduce power consumption, some modules are set to the module standby states in the initial state in this LSI. Therefore, the module standby states should be cancelled to activate these modules. For details, see section 17, Power-Down Modes. Rev.2.00 Sep. 27, 2007 Page 46 of 448 REJ09B0394-0200 4. Clock Pulse Generator Section 4 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (), internal clock (/2 to /8192, P/2 to P/1024), and peripheral clock (P). The CPG consists of an oscillator, PLL circuit, and prescaler. A block diagram of the clock pulse generator is shown in figure 4.1. The frequency from the oscillator can be modified by the PLL circuit. PLLCAP EXTAL Oscillator XTAL PLL circuit Clock divider (x 1/2) Prescaler MD2 MD3 Prescaler Clock mode control circuitry /2 to /8192 P/2 to P/1024 P Within the LSI Figure 4.1 Block Diagram of Clock Pulse Generator 4.1 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 Connecting Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.1. Use an AT-cut parallel-resonance type crystal resonator that has a resonance frequency of 4 to 10 MHz. It is recommended to consult crystal dealer concerning the compatibility of the crystal resonator and the LSI. CPG0100A_010020030200 Rev.2.00 Sep. 27, 2007 Page 47 of 448 REJ09B0394-0200 4. Clock Pulse Generator CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 18-22 pF (Recommended value) Figure 4.2 Connection of Crystal Resonator (Example) Table 4.1 Damping Resistance Values 4 500 8 200 10 0 Frequency (MHz) Rd () Crystal Resonator: Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.2. CL L XTAL C0 Rs EXTAL AT-cut parallel-resonance type Figure 4.3 Crystal Resonator Equivalent Circuit Table 4.2 Crystal Resonator Characteristics 4 120 7 8 80 7 10 60 7 Frequency (MHz) Rs max () C0 max (pF) Rev.2.00 Sep. 27, 2007 Page 48 of 448 REJ09B0394-0200 4. Clock Pulse Generator 4.1.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it in standby mode. During operation, make the external input clock frequency 4 to 10 MHz. When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing standby mode, in order to ensure the PLL stabilization time. EXTAL XTAL Open state External clock input Figure 4.4 Example of External Clock Connection 4.2 Function for Detecting Oscillator Halt This CPG can detect a clock halt and automatically cause the timer pins to become highimpedance when any system abnormality causes the oscillator to halt. That is, when a change of EXTAL has not been detected, the high-current six pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, and PE15/TIOC4D/IRQOUT) are set to high-impedance regardless of PFC setting. Even in standby mode, these six pins become high-impedance regardless of PFC setting. These pins enter the normal state after standby mode is released. When abnormalities that halt the oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI operations, including these six pins, become undefined even when the oscillator operation starts again. Rev.2.00 Sep. 27, 2007 Page 49 of 448 REJ09B0394-0200 4. Clock Pulse Generator 4.3 4.3.1 Usage Notes Note on Crystal Resonator A sufficient evaluation at the user's site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user's board design. As the resonator circuit ratings will depend on the resonator and the floating capacitance of the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. Ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 4.3.2 Notes on Board Design Measures against radiation noise are taken in this LSI. If radiation noise needs to be further reduced, usage of a multi-layer printed circuit board with ground planes is recommended. When using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 4.5 Cautions for Oscillator Circuit System Board Design A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVCL, PLLVSS, VCC, and VSS from the board power supply source, and be sure to insert bypass capacitors CB close to the pins. Rev.2.00 Sep. 27, 2007 Page 50 of 448 REJ09B0394-0200 4. Clock Pulse Generator R1: 3 k PLLCAP PLLVCL C1: 470 pF CPB = 0.47 F* PLLVSS VCC CB = 0.47 F* VSS (Values are recommended values.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry around PLL Electromagnetic waves are radiated from an LSI in operation. This LSI has an electromagnetic peak in the harmonics band whose primary frequency is determined by the lower frequency between the system clock () and peripheral clock (P). For example, when = 40 MHz and P = 40 MHz, the primary frequency is 40 MHz. If this LSI is used adjacent to a device sensitive to electromagnetic interference, e.g. FM/VHF band receiver, a printed circuit board of more than four layers with planes exclusively for system ground is recommended. Rev.2.00 Sep. 27, 2007 Page 51 of 448 REJ09B0394-0200 4. Clock Pulse Generator Rev.2.00 Sep. 27, 2007 Page 52 of 448 REJ09B0394-0200 5. Exception Processing Section 5 Exception Processing 5.1 5.1.1 Overview Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority. Table 5.1 Exception Reset Types of Exception Processing and Priority Source Power-on reset Manual reset Priority High Address error Interrupt CPU address error NMI IRQ On-chip peripheral modules: Multifunction timer unit (MTU) A/D converter 0 and 1 (A/D0, A/D1) Compare match timer 0 and 1 (CMT0, CMT1) Watchdog timer (WDT) Input/output port (I/O) (MTU) Serial communication interface 2 and 3 (SCI2, SCI3) Trap instruction (TRAPA instruction) * * * * * * Instructions General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delayed 1 2 branch instruction* or instructions that rewrite the PC* ) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, and BRAF. Rev.2.00 Sep. 27, 2007 Page 53 of 448 REJ09B0394-0200 5. Exception Processing 5.1.2 Exception Processing Operations The exception processing sources are detected and the processing starts according to the timing shown in table 5.2. Table 5.2 Exception Reset Timing for Exception Source Detection and Start of Exception Processing Source Power-on reset Manual reset Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high or when WDT overflows. Starts when the MRES pin changes from low to high. Detected when instruction is decoded and starts when the execution of the previous instruction is completed. Trap instruction General illegal instructions Illegal slot instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. Address error Interrupts Instructions When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Processing Vector Table, for more information. H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3 to I0). For address error and instruction exception processing, the I3 to I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. Rev.2.00 Sep. 27, 2007 Page 54 of 448 REJ09B0394-0200 5. Exception Processing 5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) 0 1 2 3 4 5 6 7 8 CPU address error (Reserved by system) Interrupts NMI (Reserved by system) (Reserved by system) (Reserved by system) (Reserved by system) 9 10 11 12 13 14 15 : 31 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 H'00000038 to H'0000003B H'0000003C to H'0000003F : H'0000007C to H'0000007F Exception Sources Power-on reset Rev.2.00 Sep. 27, 2007 Page 55 of 448 REJ09B0394-0200 5. Exception Processing Exception Sources Trap instruction (user vector) Vector Numbers 32 : 63 Interrupts IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system On-chip peripheral module * 64 65 66 67 68 69 70 71 72 : 255 Note: * Vector Table Address Offset H'00000080 to H'00000083 : H'000000FC to H'000000FF H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F H'00000120 to H'00000124 : H'000003FC to H'000003FF The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller (INTC), and table 6.2, Interrupt Exception Processing Vectors and Priorities. Table 5.4 Calculating Exception Processing Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Rev.2.00 Sep. 27, 2007 Page 56 of 448 REJ09B0394-0200 5. Exception Processing 5.2 5.2.1 Resets Types of Reset Resets have the highest priority of any exception source. There are two types of resets: manual resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset Status WDT Overflow MRES Overflow High Low Internal Status On-Chip Peripheral Module Initialized Initialized Type Power-on reset RES Low High CPU/INTC Initialized Initialized Initialized PFC, IO Port Initialized Not initialized Manual reset High Not initialized Not initialized 5.2.2 Power-On Reset Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a poweron reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 25 tcyc when the clock circuit is running. During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset status. In the power-on reset status, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU will then operate as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception processing vector table are set in PC and SP, then the program begins executing. Rev.2.00 Sep. 27, 2007 Page 57 of 448 REJ09B0394-0200 5. Exception Processing Be certain to always perform power-on reset processing when turning the system power on. Power-On Reset by WDT: When a setting is made for a power-on reset to be generated in the WDT's watchdog timer mode, and the WDT's TCNT overflows, the LSI becomes to be a poweron reset state. The pin function controller (PFC) registers and I/O port registers are not initialized by the reset signal generated by the WDT (these registers are initialized only by a power-on reset from outside of the chip). If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When WDT-initiated power-on reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, then the program begins executing. 5.2.3 Manual Reset When the RES pin is high and the MRES pin is driven low, the LSI enters a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the oscillation settling time that is set in WDT in standby mode (when the clock is halted) or at least 25 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters manual reset status in the middle of a bus cycle, manual reset exception processing does not start until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus cycle ends. (Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets. Rev.2.00 Sep. 27, 2007 Page 58 of 448 REJ09B0394-0200 5. Exception Processing 5.3 5.3.1 Address Errors Cause of Address Error Exception Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Instruction fetched from external memory space when in single chip mode Data read/write CPU Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* External memory space accessed when in single chip mode Note: * Address Errors None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) Address error occurs Address error occurs See section 7, Bus State Controller (BSC) for more information on the on-chip peripheral module space. Rev.2.00 Sep. 27, 2007 Page 59 of 448 REJ09B0394-0200 5. Exception Processing 5.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends, the current instruction finishes, and then address error exception processing starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The start address of the exception service routine is fetched from the exception processing vector table that corresponds to the occurred address error, and the program starts executing from that address. The jump in this case is not a delayed branch. 5.4 5.4.1 Interrupts Interrupt Sources Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, IRQ and on-chip peripheral modules. Table 5.7 Type NMI IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) IRQ0 to IRQ3 pins (external input) Multifunction timer unit Compare match timer A/D converter (A/D0 and A/D1) Serial communication interface Watchdog timer Input/output port Number of Sources 1 4 23 2 2 8 1 1 Each interrupt source is allocated a different vector number and vector table offset. See section 6, Interrupt Controller (INTC), and table 6.2, Interrupt Exception Processing Vectors and Priorities, for more information on vector numbers and vector table address offsets. Rev.2.00 Sep. 27, 2007 Page 60 of 448 REJ09B0394-0200 5. Exception Processing 5.4.2 Interrupt Priority Level The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception processing according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority registers A, D to I (IPRA, IPRD to IPRI) as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.4, Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI), for more information on IPRA, IPRD to IPRI. Table 5.8 Type NMI IRQ On-chip peripheral module Interrupt Priority Priority Level 16 0 to 15 Comment Fixed priority level. Cannot be masked. Set with interrupt priority registers A, D to I (IPRA, IPRD to IPRI). 5.4.3 Interrupt Exception Processing When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.6, Operation, for more information on the interrupt exception processing. Rev.2.00 Sep. 27, 2007 Page 61 of 448 REJ09B0394-0200 5. Exception Processing 5.5 5.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Type Trap instruction Illegal slot instructions Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that rewrite the PC Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF General illegal instructions Undefined code anywhere besides in a delay slot 5.5.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start address of the exception service routine from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction, jumps to that address and starts executing the program. This jump is not a delayed branch. Rev.2.00 Sep. 27, 2007 Page 62 of 448 REJ09B0394-0200 5. Exception Processing 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception processing starts after the undefined code is decoded. Illegal slot exception processing also starts when an instruction that rewrites the program counter (PC) is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception service routine is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump in this case is not a delayed branch. 5.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. Rev.2.00 Sep. 27, 2007 Page 63 of 448 REJ09B0394-0200 5. Exception Processing 5.6 Cases when Exception Sources are Not Accepted When an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. In this case, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction* 1 2 Address Error Not accepted Accepted Interrupt Not accepted Not accepted Immediately after an interrupt-disabled instruction* Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 5.6.1 Immediately after Delayed Branch Instruction When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction placed immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after Interrupt-Disabled Instruction When an instruction placed immediately after an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors can be accepted. Rev.2.00 Sep. 27, 2007 Page 64 of 448 REJ09B0394-0200 5. Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is shown in table 5.11. Table 5.11 Stack Status after Exception Processing Ends Types Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Stack Status Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits General illegal instruction SP Address of instruction after general illegal instruction 32 bits SR 32 bits Interrupt SP Address of instruction after executed instruction 32 bits SR 32 bits Illegal slot instruction SP Jump destination address of delay branch instruction 32 bits SR 32 bits Rev.2.00 Sep. 27, 2007 Page 65 of 448 REJ09B0394-0200 5. Exception Processing 5.8 5.8.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the value of the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start after the first exception processing is ended. Address errors will also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the service routine for address error exception and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the value of SP is reduced by 4 for both of SR and PC, therefore the value of SP is still not a multiple of four after the stacking. The address value output during stacking is the SP value, so the address itself where the error occurred is output. This means that the write data stacked is undefined. Rev.2.00 Sep. 27, 2007 Page 66 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features * 16 levels of interrupt priority * NMI noise canceler function * Occurrence of interrupt can be reported externally (IRQOUT pin) Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 MTU CMT A/D SCI WDT I/O CPU request determination Priority determination Input control Comparator Interrupt request SR I3 I2 I1 I0 CPU (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) ICR1 ICR2 ISR IPR IPRA to IPRI Internal bus Module bus Bus interface INTC Legend: MTU : Multifunction timer unit CMT : Compare match timer A/D : A/D converter SCI : Serial communications interface WDT : Watchdog timer I/O : I/O port (Port output controller) ICR1, ICR2 : Interrupt control register ISR : IRQ status register IPRA, IPRD to IPRI : Interrupt priority registers A, D to I SR : Status register Figure 6.1 INTC Block Diagram Rev.2.00 Sep. 27, 2007 Page 67 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin Pin Configuration Abbreviation NMI IRQ0 to IRQ3 IRQOUT I/O I I O Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals Output of notification signal when an interrupt has occurred 6.3 Register Descriptions The interrupt controller has the following registers. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Interrupt control register 1 (ICR1) * Interrupt control register 2 (ICR2) * IRQ status register (ISR) * Interrupt priority register A (IPRA) * Interrupt priority register D (IPRD) * Interrupt priority register E (IPRE) * Interrupt priority register F (IPRF) * Interrupt priority register G (IPRG) * Interrupt priority register H (IPRH) * Interrupt priority register I (IPRI) Rev.2.00 Sep. 27, 2007 Page 68 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin. Bit 15 Bit Name NMIL Initial Value 1/0 R/W R Description NMI Input Level Sets the level of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: NMI input level is low 1: NMI input level is high 14 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select 0: Interrupt request is detected on falling edge of NMI input (Initial value) 1: Interrupt request is detected on rising edge of NMI input 7 IRQ0S 0 R/W IRQ0 Sense Select This bit sets the IRQ0 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ0 input 1: Interrupt request is detected on edge of IRQ0 input (edge direction is selected by ICR2) 6 IRQ1S 0 R/W IRQ1 Sense Select This bit sets the IRQ1 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ1 input 1: Interrupt request is detected on edge of IRQ1 input (edge direction is selected by ICR2) 5 IRQ2S 0 R/W IRQ2 Sense Select This bit sets the IRQ2 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ2 input 1: Interrupt request is detected on edge of IRQ2 input (edge direction is selected by ICR2) Rev.2.00 Sep. 27, 2007 Page 69 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Initial Value 0 Bit 4 Bit Name IRQ3S R/W R/W Description IRQ3 Sense Select This bit sets the IRQ3 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ3 input 1: Interrupt request is detected on edge of IRQ3 input (edge direction is selected by ICR2) 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6.3.2 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0 to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1 (ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the setting of ICR2 is ignored. Bit 15 14 Bit Name IRQ0ES1 IRQ0ES0 Initial Value 0 0 R/W R/W R/W Description This bit sets the IRQ0 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ0 input 01: Interrupt request is detected on rising edge of IRQ0 input 10: Interrupt request is detected on both of falling and rising edge of IRQ0 input 11: Cannot be set Rev.2.00 Sep. 27, 2007 Page 70 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Initial Value 0 0 Bit 13 12 Bit Name IRQ1ES1 IRQ1ES0 R/W R/W R/W Description This bit sets the IRQ1 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ1 input 01: Interrupt request is detected on rising edge of IRQ1 input 10: Interrupt request is detected on both of falling and rising edge of IRQ1 input 11: Cannot be set 11 10 IRQ2ES1 IRQ2ES0 0 0 R/W R/W This bit sets the IRQ2 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ2 input 01: Interrupt request is detected on rising edge of IRQ2 input 10: Interrupt request is detected on both of falling and rising edge of IRQ2 input 11: Cannot be set 9 8 IRQ3ES1 IRQ3ES0 0 0 R/W R/W This bit sets the IRQ3 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ3 input 01: Interrupt request is detected on rising edge of IRQ3 input 10: Interrupt request is detected on both of falling and rising edge of IRQ3 input 11: Cannot be set 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev.2.00 Sep. 27, 2007 Page 71 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.3.3 IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading IRQnF = 1. Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 IRQ0F IRQ1F IRQ2F IRQ3F 0 0 0 0 R/W R/W R/W R/W IRQ0 to IRQ3 Flags These bits display the IRQ0 to IRQ3 interrupt request status. [Setting condition] * When interrupt source that is selected by ICR1 and ICR2 has occurred. [Clearing conditions] * * When 0 is written after reading IRQnF = 1 When interrupt exception processing has been executed at high level of IRQn input under the low level detection mode. When IRQn interrupt exception processing has been executed under the edge detection mode of falling edge, rising edge or both of falling and rising edge. * 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev.2.00 Sep. 27, 2007 Page 72 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.3.4 Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI) Interrupt priority registers are seven 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.2 Interrupt Exception Processing Vectors and Priorities. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000.) Bit 15 14 13 12 Bit Name IPR15 IPR14 IPR13 IPR12 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Rev.2.00 Sep. 27, 2007 Page 73 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Initial Value 0 0 0 0 Bit 11 10 9 8 Bit Name IPR11 IPR10 IPR9 IPR8 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) 7 6 5 4 IPR7 IPR6 IPR5 IPR4 0 0 0 0 R/W R/W R/W R/W These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Rev.2.00 Sep. 27, 2007 Page 74 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Initial Value 0 0 0 0 Bit 3 2 1 0 Bit Name IPR3 IPR2 IPR1 IPR0 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name. 6.4 6.4.1 Interrupt Sources External Interrupts There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Set the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register 1 (ICR1) and IRQ edge select bit (IRQ0ES[1:0] to IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select low level detection, falling edge detection, or rising edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority register A (IPRA). Rev.2.00 Sep. 27, 2007 Page 75 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F to IRQ3F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of this IRQ3 to IRQ0 interrupts. IRQnS IRQnES ISR.IRQnF Selection IRQ pins Level detection Edge detection S Q CPU interrupt request RESIRQn R (Acceptance of IRQn interrupt/writing 0 after reading IRQnF = 1) Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control Rev.2.00 Sep. 27, 2007 Page 76 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. As a different interrupt vector is assigned to each interrupt source, the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers A, D to I (IPRA, IPRD to IPRI). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.5 Interrupt Exception Processing Vectors Table Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. For the details of calculation of vector table address, see table 5.4, Calculating Exception Processing Vector Table Addresses in the section 5 Exception Processing. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A, D to I (IPRA, IPRD to IPRI). However, the smaller vector number has interrupt source, the higher priority ranking is assigned among two or more interrupt sources specified by the same IPR, and the priority ranking cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order indicated in table 6.2. Rev.2.00 Sep. 27, 2007 Page 77 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Table 6.2 Interrupt Source External pin Interrupts Interrupt Exception Processing Vectors and Priorities Name NMI Reserved by system Reserved by system Reserved by system IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system Vector No. 11 12 14 15 64 65 66 67 68 69 70 71 72 76 80 84 88 89 90 91 92 96 97 100 101 Vector Table Starting Address H'0000002C H'00000030 H'00000038 H'0000003C H'00000100 H'00000104 H'00000108 H'0000010C H'00000110 H'00000114 H'00000118 H'0000011C H'00000120 H'00000130 H'00000140 H'00000150 H'00000160 H'00000164 H'00000168 H'0000016C H'00000170 H'00000180 H'00000184 H'00000190 H'00000194 IPRD3 to IPRD0 Low IPRD11 to IPRD8 IPRD7 to IPRD4 IPR IPRA15 to IPRA12 IPRA11 to IPRA8 IPRA7 to IPRA4 IPRA3 to IPRA0 IPRD15 to IPRD12 Default Priority High Reserved by system Reserved by system Reserved by system Reserved by system MTU channel 0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 MTU channel 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 Rev.2.00 Sep. 27, 2007 Page 78 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Interrupt Source Vector No. 104 105 108 109 112 113 114 115 116 120 121 122 123 124 128 to 135 136 137 140 144 148 152 153 156 160 to 167 168 169 170 171 Vector Table Starting Address H'000001A0 H'000001A4 H'000001B0 H'000001B4 H'000001C0 H'000001C4 H'000001C8 H'000001CC H'000001D0 H'000001E0 H'000001E4 H'000001E8 H'000001EC H'000001F0 H'00000200 to H'0000021C H'00000220 H'00000224 H'00000230 H'00000240 H'00000250 H'00000260 H'00000264 H'00000270 H'00000290 to H'0000029C H'000002A0 H'000002A4 H'000002A8 H'000002AC Low IPRF11 to IPRF8 IPRG15 to IPRG12 IPRG7 to IPRG4 IPRG3 to IPRG0 IPRH15 to IPRH12 IPRH11 to IPRH8 IPRI15 to IPRI12 IPRE3 to IPRE0 IPRF15 to IPRF12 IPRE7 to IPRE4 Default Priority High Name IPR IPRE15 to IPRE12 IPRE11 to IPRE8 MTU channel 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 MTU channel 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 MTU channel 4 TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 A/D CMT Reserved by system ADI0 ADI1 Reserved by system CMI0 CMI1 Watchdog timer I/O (MTU) SCI channel 2 ITI Reserved by system MTUPOE Reserved by system ERI_2 RXI_2 TXI_2 TEI_2 Rev.2.00 Sep. 27, 2007 Page 79 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Interrupt Source SCI channel 3 Vector No. 172 173 174 175 176 177 178 179 180 181 184 188 to 196 200 204 208 209 210 211 212 Vector Table Starting Address H'000002B0 H'000002B4 H'000002B8 H'000002BC H'000002C0 H'000002C4 H'000002C8 H'000002CC H'000002D0 H'000002D4 H'000002E0 H'000002F0 to H'00000310 H'00000320 H'00000330 H'00000340 H'00000344 H'00000348 H'0000034C H'00000350 to H'000003DC Low Default Priority High Name ERI_3 RXI_3 TXI_3 TEI_3 IPR IPRI11 to IPRI8 Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Rev.2.00 Sep. 27, 2007 Page 80 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.6 6.6.1 Operation Interrupt Sequence The sequence of interrupt operations is explained below. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, according to the priority levels set in interrupt priority registers A, D to I (IPRA, IPRD to IPRI). Interrupts that have lower-priority than that of the selected interrupt are ignored.* If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority order indicated in table 6.2. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.5). 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR). 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in (5) above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepting, the IRQOUT pin holds low level. 9. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program. This jump is not a delay branch. Note: * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. Rev.2.00 Sep. 27, 2007 Page 81 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Program execution state Interrupt? Yes NMI? Yes No No Level 15 interrupt? Yes Yes I3 to I0 level 14? No Yes No Level 14 interrupt? Yes I3 to I0 level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No IRQOUT = low Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 IRQOUT = high Read exception vector table Branch to exception service routine *1 *2 Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU 1. IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1). Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3-I0 of SR. 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the CPU, the IRQOUT pin holds low level. Figure 6.3 Interrupt Sequence Flowchart Rev.2.00 Sep. 27, 2007 Page 82 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n-8 4n-4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Processing Rev.2.00 Sep. 27, 2007 Page 83 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) 6.7 Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an IRQ interrupt is accepted. Table 6.3 Interrupt Response Time Number of States Item Idle cycle Interrupt priority judgment and comparison with SR mask bits Wait for completion of sequence currently being executed by CPU NMI, Peripheral Module 0 or 1 2 IRQ 1 3 Remarks X ( 0) X ( 0) The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the saving PC and SR, and vector address fetch. Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt response time Total: (7 or 8) + m1 + m2 + m3 + X Minimum: 10 Maximum: 12 + 2 (m1 + m2 + m3) + m4 Note: * 5 + m1 + m2 + m3 9 + m1 + m2 + m3 + X 12 13 + 2 (m1 + m2 + m3) + m4 0.25 to 0.28 s 0.48 s* 0.48 s at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1. m1 to m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev.2.00 Sep. 27, 2007 Page 84 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Interrupt acceptance 5 + m1 + m2 + m3 1 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F D E E MM E M E E 3 3 m1 m2 1 m3 1 F F D E Legend: F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted Rev.2.00 Sep. 27, 2007 Page 85 of 448 REJ09B0394-0200 6. Interrupt Controller (INTC) Rev.2.00 Sep. 27, 2007 Page 86 of 448 REJ09B0394-0200 7. Bus State Controller (BSC) Section 7 Bus State Controller (BSC) The bus state controller (BSC) controls accesses to the on-chip ROM, RAM, and peripheral module registers. 7.1 Features The BSC has the following features: * On-chip ROM and RAM interfaces On-chip ROM and RAM access of 32 bits in 1 state * Accesses to on-chip peripheral module registers 7.2 Input/output Pin There are no pins corresponding to this function. 7.3 Register The BSC has the following register. For details on these register addresses and register states in each processing states, refer to section 18, List of Registers. * Bus control register 1 (BCR1) BSC1000A_010020030200 Rev.2.00 Sep. 27, 2007 Page 87 of 448 REJ09B0394-0200 7. Bus State Controller (BSC) 7.4 Address Map Table 7.1 shows the address map. Table 7.1 Address Map On-chip ROM enabled mode Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0001 FFFF H'0002 0000 to H'0003 FFFF H'0004 0000 to H'FFFF 7FFF Reserved Reserved On-chip peripheral module Reserved On-chip RAM Reserved Reserved 2 kbytes 32 bits 32 bits 32 bits Space On-chip ROM Memory On-chip ROM Size 32 kbytes Reserved Reserved Reserved 16 kbytes 8, 16 bits Bus Width 32 bits 32 bits 32 bits H'FFFF 8000 to H'FFFF BFFF On-chip peripheral module H'FFFF C000 to H'FFFF CFFF Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF F7FF H'FFFF F800 to H'FFFF FFFF Note: Reserved area should not be accessed, or operation cannot be guaranteed. Rev.2.00 Sep. 27, 2007 Page 88 of 448 REJ09B0394-0200 7. Bus State Controller (BSC) 7.5 7.5.1 Register Description Bus Control Register 1 (BCR1) BCR1 is a 16-bit readable/writable register that enables access to the MTU control registers. Bit 15 Bit Name Initial Value 0 R/W R Description Reserved These bits are always read as 0 and should always be written to 0. 14 1 R Reserved These bits are always read as 1 and should always be written to 1. 13 MTURWE 1 R/W MTU Read/Write Enable This bit enables MTU control register access. For details, refer to MTU section. 0: MTU control register access is disabled 1: MTU control register access is enabled 12 to 8 All 0 R Reserved These bits are always read as 0 and the write value should always be 0. 7 to 4 All 0 R Reserved These bits are always read as 0 and the write value should always be 0. 3 to 0 All 1 R Reserved These bits are always read as 1 and the write value should always be 1. Rev.2.00 Sep. 27, 2007 Page 89 of 448 REJ09B0394-0200 7. Bus State Controller (BSC) 7.6 On-chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 7.2. Table 7.2 On-chip Peripheral I/O Register Access SCI 8 bits 1 On-chip Peripheral Module Connected bus width Access cycle MTU, POE 16 bits 1 INTC 16 bits 2 PFC, PORT 16 bits 2 CMT 16 bits 1 A/D 8 bits 1 WDT 16 bits 2 2 cycles* 2 cycles* 2 cycles* 2 cycles* 2 cycles* 3 cycles* 3 cycles* Notes: 1. In terms of the peripheral clock value 2. In terms of the system clock value Rev.2.00 Sep. 27, 2007 Page 90 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Section 8 Multi-Function Timer Pulse Unit (MTU) This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 8.1. 8.1 Features * Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 12-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0, 3, and 4 * Phase counting mode settable independently for each of channels 1 and 2 * Cascade connection operation * Fast access via internal 16-bit bus * 23 interrupt sources * Automatic transfer of register data * A/D converter conversion start trigger can be generated * Module standby mode can be set * Positive and negative 3-phase waveforms (6-phase waveforms in total) can be output in complementary or reset synchronous PWM mode by combining channels 3 and 4. * AC synchronous motor (brushless DC motor) can be driven in complementary or reset synchronous PWM mode by combining channels 0, 3, and 4. Chopping or level output can be selected as drive waveform output. TIMMTU0A_010020030200 Rev.2.00 Sep. 27, 2007 Page 91 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.1 Item Count clock MTU Functions Channel 0 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture Channel 1 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TGRA_1 TGRB_1 TIOC1A TIOC1B Channel 2 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOC2A TIOC2B Channel 3 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOC3A TIOC3B TIOC3C TIOC3D TGR compare match or input capture Channel 4 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D TGR compare match or input capture General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset synchronous PWM mode AC synchronous motor drive mode Rev.2.00 Sep. 27, 2007 Page 92 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Item Phase counting mode Buffer operation A/D converter start trigger TGRA_0 compare match or input capture 5 sources * Compare match or input capture 0A * Compare match or input capture 0B * Compare match or input capture 0C * Compare match or input capture 0D * Overflow Channel 0 TGRA_1 compare match or input capture 4 sources * Compare match or input capture 1A * Compare match or input capture 1B * Overflow * Underflow TGRA_2 compare match or input capture 4 sources TGRA_3 compare match or input capture 5 sources TGRA_4 compare match or input capture 5 sources Channel 1 Channel 2 Channel 3 Channel 4 Interrupt sources * Compare * Compare * Compare match or match or match or input input input capture 2A capture 3A capture 4A * Compare * Compare * Compare match or match or match or input input input capture 2B capture 3B capture 4B * Overflow * Compare * Compare match or match or * Underflow input input capture 4C capture 3C * Compare * Compare match or match or input input capture 4D capture 3D * Underflow/ * Overflow Overflow Legend: : Possible : Not possible Rev.2.00 Sep. 27, 2007 Page 93 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TIORL TMDR Channel 3 TSR TGRC TGRD TGRB TGRA TCNT Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Control logic for channels 3 and 4 Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TGI4C TGI4D TCI4V TIORH TIORL TMDR Channel 4 TSR TIER TCR TGRC TDDR TIORH TGCR TOCR TIER TCR TCNTS TCDR TMDR Channel 2 TSR Clock input P/1 Internal clock: P/4 P/16 P/64 P/256 P/1024 External clock: TCLKA TCLKB TCLKC TCLKD TOER TCBR TGRD TGRB TGRA TCNT TSYR Module data bus Internal data bus Control logic Common BUS I/F TSTR A/D converter conversion start signal TIOR Control logic for channel 0 to 2 TIER TCR TGRB TGRA TCNT TIORL TMDR Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B Channel 0 TGRC TIORH Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): TIER TCR Timer start register Timer synchro register Timer control register Timer mode register Timer I/O control registers (H, L) Timer interrupt enable register TIER: Timer status register TSR: Timer counter TCNT: TGR (A, B, C, D): Timer general registers (A, B, C, D) Figure 8.1 Block Diagram of MTU Rev.2.00 Sep. 27, 2007 Page 94 of 448 REJ09B0394-0200 TGRD TGRB TGRA TCNT Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TIOR TSR TIER TCR TGRB TGRA TCNT 8. Multi-Function Timer Pulse Unit (MTU) 8.2 Table 8.2 Channel All Input/Output Pins Pin configuration Symbol TCLKA TCLKB TCLKC TCLKD I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 TIOC1A TIOC1B 2 TIOC2A TIOC2B 3 TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D Rev.2.00 Sep. 27, 2007 Page 95 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3 Register Descriptions The MTU has the following registers. For details on register addresses and register states during each process, refer to section 18, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. * Timer control register_0 (TCR_0) * Timer mode register_0 (TMDR_0) * Timer I/O control register H_0 (TIORH_0) * Timer I/O control register L_0 (TIORL_0) * Timer interrupt enable register_0 (TIER_0) * Timer status register_0 (TSR_0) * Timer counter_0 (TCNT_0) * Timer general register A_0 (TGRA_0) * Timer general register B_0 (TGRB_0) * Timer general register C_0 (TGRC_0) * Timer general register D_0 (TGRD_0) * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register _1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) * Timer control register_3 (TCR_3) Rev.2.00 Sep. 27, 2007 Page 96 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) * Timer mode register_3 (TMDR_3) * Timer I/O control register H_3 (TIORH_3) * Timer I/O control register L_3 (TIORL_3) * Timer interrupt enable register_3 (TIER_3) * Timer status register_3 (TSR_3) * Timer counter_3 (TCNT_3) * Timer general register A_3 (TGRA_3) * Timer general register B_3 (TGRB_3) * Timer general register C_3 (TGRC_3) * Timer general register D_3 (TGRD_3) * Timer control register_4 (TCR_4) * Timer mode register_4 (TMDR_4) * Timer I/O control register H_4 (TIORH_4) * Timer I/O control register L_4 (TIORL_4) * Timer interrupt enable register_4 (TIER_4) * Timer status register_4 (TSR_4) * Timer counter_4 (TCNT_4) * Timer general register A_4 (TGRA_4) * Timer general register B_4 (TGRB_4) * Timer general register C_4 (TGRC_4) * Timer general register D_4 (TGRD_4) Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR) Common Registers for timers 3 and 4 * Timer output master enable register (TOER) * Timer output control enable register (TOCR) * Timer gate control register (TGCR) * Timer cycle data register (TCDR) * Timer dead time data register (TDDR) * Timer subcounter (TCNTS) * Timer cycle buffer register (TCBR) Rev.2.00 Sep. 27, 2007 Page 97 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings should be conducted only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 8.3 and 8.4 for details. Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P /4 both edges = /2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P /4 or slower. When P /1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges Legend: X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 8.5 to 8.8 for details. Rev.2.00 Sep. 27, 2007 Page 98 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.3 Channel 0, 3, 4 CCLR0 to CCLR2 (channels 0, 3, and 4) Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 0 0 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 8.4 Channel 1, 2 CCLR0 to CCLR2 (channels 1 and 2) Bit 7 Bit 6 2 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0. Writing is ignored. Rev.2.00 Sep. 27, 2007 Page 99 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.5 Channel 0 TPSC0 to TPSC2 (channel 0) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 8.6 Channel 1 TPSC0 to TPSC2 (channel 1) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT_2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev.2.00 Sep. 27, 2007 Page 100 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.7 Channel 2 TPSC0 to TPSC2 (channel 2) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 8.8 Channel 3, 4 TPSC0 to TPSC2 (channels 3 and 4) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 Internal clock: counts on P/256 Internal clock: counts on P/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Rev.2.00 Sep. 27, 2007 Page 101 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit 7, 6 Bit Name Initial value All 1 R/W Description Reserved These bits are always read as 1, and should only be written with 1. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0, and the write value should always be 0. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0, and the write value should always be 0. 0: TGRA and TGRD operate normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 8.9 for details. Rev.2.00 Sep. 27, 2007 Page 102 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.9 Bit 3 MD3 0 MD0 to MD3 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2* 1 2 2 2 2 3 Phase counting mode 1* Phase counting mode 2* Phase counting mode 3* Phase counting mode 4* 1 0 0 0 1 Reset synchronous PWM mode* Reserved (do not set) Reserved (do not set) Reserved (do not set) 1 1 0 X 0 1 Complementary PWM mode 1 (transmit at peak)* 3 3 3 1 0 1 Complementary PWM mode 2 (transmit at valley)* Complementary PWM mode 2 (transmit at peak and valley)* Legend: X: Don't care Notes: 1. PWM mode 2 can not be set for channels 3, 4. 2. Phase counting mode can not be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode can not be set for channels 0, 1, and 2. Rev.2.00 Sep. 27, 2007 Page 103 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit 7 6 5 4 Bit Name IOB3 IOB2 IOB1 IOB0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 8.10 Table 8.14 Table 8.16 Table 8.18 Table 8.22 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R/W R/W R/W R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 8.11 Table 8.15 Table 8.17 Table 8.19 Table 8.23 Rev.2.00 Sep. 27, 2007 Page 104 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TIORL_0, TIORL_3, TIORL_4 Bit 7 6 5 4 Bit Name IOD3 IOD2 IOD1 IOD0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control D0 to D3 Specify the function of TGRD. When the TGRD is used as a buffer register of the TGRB, this setting is invalid and input capture/output compare is not generated. See the following tables. TIORL_0: Table 8.12 TIORL_3: Table 8.20 TIORL_4: Table 8.24 3 2 1 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 R/W R/W R/W R/W I/O Control C0 to C3 Specify the function of TGRC. When the TGRC is used as a buffer register of the TGRA, this setting is invalid and input capture/output compare is not generated. See the following tables. TIORL_0: Table 8.13 TIORL_3: Table 8.21 TIORL_4: Table 8.25 Rev.2.00 Sep. 27, 2007 Page 105 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.10 TIORH_0 (channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: X: Don't care X X X Input capture register TGRB_0 Function Output compare register TIOC0B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down Rev.2.00 Sep. 27, 2007 Page 106 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.11 TIORH_0 (channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: X: Don't care X X X Input capture register TGRA_0 Function Output compare register TIOC0A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Rev.2.00 Sep. 27, 2007 Page 107 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.12 TIORL_0 (channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register* TGRD_0 Function Output compare register* TIOC0D Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: X: Don't care Note: * When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Sep. 27, 2007 Page 108 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.13 TIORL_0 (channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register* TGRC_0 Function Output compare register* TIOC0C Pin Function Output disable Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: X: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Sep. 27, 2007 Page 109 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.14 TIOR_1 (channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: X: Don't care X X X Input capture register TGRB_1 Function Output compare register TIOC1B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture Rev.2.00 Sep. 27, 2007 Page 110 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.15 TIOR_1 (channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: X: Don't care X X X Input capture register TGRA_1 Function Output compare register TIOC1A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture Rev.2.00 Sep. 27, 2007 Page 111 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.16 TIOR_2 (channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend: X: Don't care X Input capture register TGRB_2 Function Output compare register TIOC2B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.2.00 Sep. 27, 2007 Page 112 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.17 TIOR_2 (channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend: X: Don't care X Input capture register TGRA_2 Function Output compare register TIOC2A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.2.00 Sep. 27, 2007 Page 113 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.18 TIORH_3 (channel 3) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend: X: Don't care X Input capture register TGRB_3 Function Output compare register TIOC3B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.2.00 Sep. 27, 2007 Page 114 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.19 TIORH_3 (channel 3) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend: X: Don't care X Input capture register TGRA_3 Function Output compare register TIOC3A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.2.00 Sep. 27, 2007 Page 115 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.20 TIORL_3 (channel 3) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register* TGRD_3 Function Output compare register* TIOC3D Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Sep. 27, 2007 Page 116 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.21 TIORL_3 (channel 3) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register* TGRC_3 Function Output compare register* TIOC3C Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Sep. 27, 2007 Page 117 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.22 TIORH_4 (channel 4) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend: X: Don't care X Input capture register TGRB_4 Function Output compare register TIOC4B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.2.00 Sep. 27, 2007 Page 118 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.23 TIORH_4 (channel 4) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend: X: Don't care X Input capture register TGRA_4 Function Output compare register TIOC4A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.2.00 Sep. 27, 2007 Page 119 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.24 TIORL_4 (channel 4) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRD_4 Function Output compare register* TIOC4B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Sep. 27, 2007 Page 120 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.25 TIORL_4 (channel 4) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRC_4 Function Output compare register* TIOC4C Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.2.00 Sep. 27, 2007 Page 121 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU has five TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 1 R Reserved This bit is always read as 1, and should only be written with 1. 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev.2.00 Sep. 27, 2007 Page 122 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 2 Bit Name TGIEC R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev.2.00 Sep. 27, 2007 Page 123 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU has five TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 3, and 4. In channel 0, bit 7 is reserved. It is always read as 1, and should only be written with 1. 0: TCNT counts down 1: TCNT counts up 6 1 R Reserved This bit is always read as 1, and should only be written with 1. 5 TCFU 0 R/(W) Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and the write value should always be 0. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] * 4 TCFV 0 R/(W) When 0 is written to TCFU after reading TCFU = 1 Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when TCNT_4 is underflowed (changes from H'0000 to H'0001) in complementary PWM mode. [Clearing condition] * Rev.2.00 Sep. 27, 2007 Page 124 of 448 REJ09B0394-0200 When 0 is written to TCFV after reading TCFV = 1 * * 8. Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 3 Bit Name TGFD R/W R/(W) Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and the write value should always be 0. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing condition] * 2 TGFC 0 R/(W) When 0 is written to TGFD after reading TGFD = 1 Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and the write value should always be 0. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing condition] * When 0 is written to TGFC after reading TGFC = 1 Rev.2.00 Sep. 27, 2007 Page 125 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 1 Bit Name TGFB R/W R/(W) Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing condition] * 0 TGFA 0 R/(W) When 0 is written to TGFB after reading TGFB = 1 Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing condition] * When 0 is written to TGFA after reading TGFA = 1 8.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one for each channel. The initial value is H'0000. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Rev.2.00 Sep. 27, 2007 Page 126 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.7 Timer General Register (TGR) The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3, and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRATGRC and TGRB-TGRD. The initial value is H'FFFF. 8.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 6 Bit Name CST4 CST3 Initial value 0 0 R/W R/W R/W Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 All 0 R Reserved These bits are always read as 0. Only 0 should be written to these bits. 2 1 0 CST2 CST1 CST0 0 0 0 R/W R/W R/W Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 and TCNT_0 count operation is stopped 1: TCNT_2 and TCNT_0 performs count operation Rev.2.00 Sep. 27, 2007 Page 127 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.9 Timer Synchro Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7 6 Bit Name SYNC4 SYNC3 Initial value 0 0 R/W R/W R/W Description Timer Synchro 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 All 0 R Reserved These bits are always read as 0. Only 0 should be written to these bits. Rev.2.00 Sep. 27, 2007 Page 128 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial value 0 0 0 Bit 2 1 0 Bit Name SYNC2 SYNC1 SYNC0 R/W R/W R/W R/W Description Timer Synchro 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Rev.2.00 Sep. 27, 2007 Page 129 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.10 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit 7, 6 Bit Name Initial value All 1 R/W R Description Reserved These bits are always read as 1. Only 1 should be written to these bits. Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 5 OE4D 0 R/W 4 OE4C 0 R/W 3 OE3D 0 R/W 2 OE4B 0 R/W 1 OE4A 0 R/W 0 OE3B 0 R/W Rev.2.00 Sep. 27, 2007 Page 130 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.11 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit 7 Bit Name Initial value 0 R/W R Description Reserved These bits are always read as 0. Only 0 should be written to this bit. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5 to 2 All 0 R Reserved These bits are always read as 0. Only 0 should be written to this bit. 1 OLSN 0 R/W Output Level Select N This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 8.26 0 OLSP 0 R/W Output Level Select P This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 8.27 Table 8.26 Output Level Select Function Bit 1 Function Compare Match Output OLSN 0 1 Initial Output High level Low level Active Level Low level High level Increment Count High level Low level Decrement Count Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Rev.2.00 Sep. 27, 2007 Page 131 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.27 Output Level Select Function Bit 1 Function Compare Match Output OLSP 0 1 Initial Output High level Low level Active Level Low level High level Increment Count Low level High level Decrement Count High level Low level Figure 8.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3, and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Time Positive phase output Reverse phase output Figure 8.2 Complementary PWM Mode Output Level Example Rev.2.00 Sep. 27, 2007 Page 132 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.12 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit 7 Bit Name Initial value 0 R/W R Description Reserved This bit is always read as 1. Only 1 should be written to this bit. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective 5 N 0 R/W Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are on-output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are onoutput. 0: Level output 1: Reset synchronized PWM/complementary PWM output Rev.2.00 Sep. 27, 2007 Page 133 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 3 Bit Name FB R/W R/W Description External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is carried out by external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings). 2 1 0 WF VF UF 0 0 0 R/W R/W R/W Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 8.28. Table 8.28 Output level Select Function Function Bit 2 WF 0 Bit 1 VF 0 Bit 0 UF 0 1 1 0 1 1 0 0 1 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B TIOC3D TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF W Phase U Phase OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF Rev.2.00 Sep. 27, 2007 Page 134 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.13 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value is H'0000. Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. 8.3.14 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value is H'FFFF. Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 8.3.15 Timer Period Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value is H'FFFF. Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. 8.3.16 Timer Period Buffer Register (TCBR) The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value is H'FFFF. Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. Rev.2.00 Sep. 27, 2007 Page 135 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.3.17 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register (TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. Rev.2.00 Sep. 27, 2007 Page 136 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.4 8.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always set the MTU external pins function using the pin function controller (PFC). Counter Operation When one of bits CST0 to CST4 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Example of Count Operation Setting Procedure: Figure 8.3 shows an example of the count operation setting procedure. Operation selection [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Select counter clock [1] Periodic counter Select counter clearing source Select output compare register Set period [2] [3] [4] [5] Start count operation Figure 8.3 Example of Counter Operation Setting Procedure Rev.2.00 Sep. 27, 2007 Page 137 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 8.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 8.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev.2.00 Sep. 27, 2007 Page 138 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Figure 8.5 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software TGF Figure 8.5 Periodic Counter Operation Waveform Output by Compare Match The MTU can perform 0, 1, or toggle output from the corresponding output pin using compare match. Example of Setting Procedure for Waveform Output by Compare Match: Figure 8.6 shows an example of the setting procedure for waveform output by compare match. Output selection [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Select waveform output mode [1] Start count operation [3] Figure 8.6 Example of Setting Procedure for Waveform Output by Compare Match Rev.2.00 Sep. 27, 2007 Page 139 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Examples of Waveform Output Operation: Figure 8.7 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB No change No change Time No change No change 1 output 0 output Figure 8.7 Example of 0 Output/1 Output Operation Figure 8.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle output Toggle output Figure 8.8 Example of Toggle Output Operation Rev.2.00 Sep. 27, 2007 Page 140 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. Example of Input Capture Operation Setting Procedure: Figure 8.9 shows an example of the input capture operation setting procedure. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Select input capture input [1] Start count [2] Figure 8.9 Example of Input Capture Operation Setting Procedure Rev.2.00 Sep. 27, 2007 Page 141 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Example of Input Capture Operation: Figure 8.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 8.10 Example of Input Capture Operation 8.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Rev.2.00 Sep. 27, 2007 Page 142 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation Setting Procedure: Figure 8.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 8.11 Example of Synchronous Operation Setting Procedure Rev.2.00 Sep. 27, 2007 Page 143 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation: Figure 8.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 8.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Time Figure 8.12 Example of Synchronous Operation Rev.2.00 Sep. 27, 2007 Page 144 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 8.29 shows the register combinations used in buffer operation. Table 8.29 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 4 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 8.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 8.13 Compare Match Buffer Operation Rev.2.00 Sep. 27, 2007 Page 145 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 8.14. Input capture signal Buffer register Timer general register TCNT Figure 8.14 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 8.15 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Select TGR function [1] Start count [3] Figure 8.15 Example of Buffer Operation Setting Procedure Rev.2.00 Sep. 27, 2007 Page 146 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Examples of Buffer Operation: * When TGR is an output compare register Figure 8.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 8.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 8.16 Example of Buffer Operation (1) Rev.2.00 Sep. 27, 2007 Page 147 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) * When TGR is an input capture register Figure 8.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'0532 H'09FB H'0F07 TGRC Figure 8.17 Example of Buffer Operation (2) Rev.2.00 Sep. 27, 2007 Page 148 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 8.30 shows the register combinations used in cascaded operation. Table 8.30 Cascaded Combinations Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2 Note: When phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and the counters operates independently in phase counting mode. Example of Cascaded Operation Setting Procedure: Figure 8.18 shows an example of the setting procedure for cascaded operation. Cascaded operation [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'111 to select TCNT_2 overflow/ underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Set cascading Start count [2] Figure 8.18 Cascaded Operation Setting Procedure Rev.2.00 Sep. 27, 2007 Page 149 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Examples of Cascaded Operation: Figure 8.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 8.19 Example of Cascaded Operation 8.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. Rev.2.00 Sep. 27, 2007 Page 150 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 8.31. Table 8.31 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A TIOC1A TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev.2.00 Sep. 27, 2007 Page 151 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Example of PWM Mode Setting Procedure: Figure 8.20 shows an example of the PWM mode setting procedure. PWM mode [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [3] [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] Select counter clock [1] Select counter clearing source [2] Select waveform output level Set TGR [4] Start count [6] Figure 8.20 Example of PWM Mode Setting Procedure Rev.2.00 Sep. 27, 2007 Page 152 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Examples of PWM Mode Operation: Figure 8.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty cycle. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 8.21 Example of PWM Mode Operation (1) Rev.2.00 Sep. 27, 2007 Page 153 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Figure 8.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty cycle levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 8.22 Example of PWM Mode Operation (2) Rev.2.00 Sep. 27, 2007 Page 154 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Figure 8.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty cycle Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle 0% duty cycle TGRB rewritten Time TIOCA Figure 8.23 Example of PWM Mode Operation (3) Rev.2.00 Sep. 27, 2007 Page 155 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 8.32 shows the correspondence between external clock pins and channels. Table 8.32 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Rev.2.00 Sep. 27, 2007 Page 156 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Example of Phase Counting Mode Setting Procedure: Figure 8.24 shows an example of the phase counting mode setting procedure. Phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Select phase counting mode [1] Start count [2] Figure 8.24 Example of Phase Counting Mode Setting Procedure Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 8.25 shows an example of phase counting mode 1 operation, and table 8.33 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.25 Example of Phase Counting Mode 1 Operation Rev.2.00 Sep. 27, 2007 Page 157 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count * Phase counting mode 2 Figure 8.26 shows an example of phase counting mode 2 operation, and table 8.34 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.26 Example of Phase Counting Mode 2 Operation Rev.2.00 Sep. 27, 2007 Page 158 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count Up-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care * Phase counting mode 3 Figure 8.27 shows an example of phase counting mode 3 operation, and table 8.35 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.27 Example of Phase Counting Mode 3 Operation Rev.2.00 Sep. 27, 2007 Page 159 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Up-count Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care * Phase counting mode 4 Figure 8.28 shows an example of phase counting mode 4 operation, and table 8.36 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 8.28 Example of Phase Counting Mode 4 Operation Rev.2.00 Sep. 27, 2007 Page 160 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Phase Counting Mode Application Example: Figure 8.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Rev.2.00 Sep. 27, 2007 Page 161 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 + + - TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 8.29 Phase Counting Mode Application Example Rev.2.00 Sep. 27, 2007 Page 162 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 8.37 shows the PWM output pins used. Table 8.38 shows the settings of the registers. Table 8.37 Output Pins for Reset-Synchronized PWM Mode Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3) Table 8.38 Register Settings for Reset-Synchronized PWM Mode Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Rev.2.00 Sep. 27, 2007 Page 163 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 8.30 shows an example of procedure for selecting the reset synchronized PWM mode. 1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The resetsynchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. 2. Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. 3. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4. Reset TCNT_3 and TCNT_4 to H'0000. 5. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X TGRA_3 (X: set value). 6. Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 7. Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM output pins*. Do not set to TMDR_4. 8. Set the enabling/disabling of the PWM waveform output pin in TOER. 9. Set the CST3 bit in the TSTR to 1 to start the count operation. Notes: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty cycle. * PFC registers should be specified before this procedure. Rev.2.00 Sep. 27, 2007 Page 164 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Reset-synchronized PWM mode Stop counting 1 Select counter clock and counter clear source 2 Brushless DC motor control setting 3 Set TCNT 4 Set TGR 5 PWM cycle output enabling, PWM output level setting 6 Set reset-synchronized PWM mode 7 Enable waveform output 8 Start count operation Reset-synchronized PWM mode 9 Figure 8.30 Procedure for Selecting the Reset-Synchronized PWM Mode Rev.2.00 Sep. 27, 2007 Page 165 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Reset-Synchronized PWM Mode Operation: Figure 8.31 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT_3 and TCNT_4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 8.31 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1) Rev.2.00 Sep. 27, 2007 Page 166 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as increment/decrement counters. Table 8.39 shows the PWM output pins used. Table 8.40 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 8.39 Output Pins for Complementary PWM Mode Channel 3 Output Pin TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Note: * Description Toggle output synchronized with PWM period (or I/O port) PWM output pin 1 I/O port* PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3) Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. Rev.2.00 Sep. 27, 2007 Page 167 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.40 Register Settings for Complementary PWM Mode Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Always readable/writable Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Always readable/writable Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable Access can be enabled or disabled according to the setting of bit 13 (MTURWE) in BSC/BCR1 (bus controller/bus control register 1). Rev.2.00 Sep. 27, 2007 Page 168 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TGRA_3 comparematch interrupt TCNT_4 underflow interrupt TGRC_3 TCBR TDDR TGRA_3 TCDR Comparator Output controller Match signal PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3 Comparator Match signal TGRA_4 TGRB_4 Temp 3 TGRB_3 Temp 1 TGRD_3 TGRC_4 Temp 2 TGRD_4 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by the bus controller) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 8.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode Rev.2.00 Sep. 27, 2007 Page 169 of 448 REJ09B0394-0200 Output protection circuit TCNT_3 TCNTS TCNT_4 8. Multi-Function Timer Pulse Unit (MTU) Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 8.33. 1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. 2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. 3. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4. Set the dead time in TCNT_3. Set TCNT_4 to H'0000. 5. Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). 6. Set the output PWM duty cycle in the duty cycle registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. 7. Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. 8. Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 9. Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins*. Do not set in TMDR_4. 10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). 11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Note: * PFC registers should be specified before this procedure. Rev.2.00 Sep. 27, 2007 Page 170 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Complementary PWM mode Stop count operation 1 Counter clock, counter clear source selection 2 Brushless DC motor control setting 3 TCNT setting 4 Inter-channel synchronization setting 5 TGR setting 6 Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting 7 8 9 Enable waveform output 10 Start count operation 11 Figure 8.33 Example of Complementary PWM Mode Setting Procedure Rev.2.00 Sep. 27, 2007 Page 171 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 8.34 illustrates counter operation in complementary PWM mode, and figure 8.35 shows an example of complementary PWM mode operation. Counter Operation: In complementary PWM mode, three countersTCNT_3, TCNT_4, and TCNTSperform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT_3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT_4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty cycle is set during the count operation only. Rev.2.00 Sep. 27, 2007 Page 172 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TCNT_3 TCNT_4 TCNTS Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Time TCNTS Figure 8.34 Complementary PWM Mode Counter Operation Register Operation: In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 8.35 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 8.35 shows an example in which the mode is selected in which the change is made in the trough. Rev.2.00 Sep. 27, 2007 Page 173 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) In the Tb interval (Tb1 in figure 8.35) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three countersTCNT_3, TCNT_4, and TCNTSand two registerscompare register and temporary registerare compared, and PWM output controlled accordingly. Rev.2.00 Sep. 27, 2007 Page 174 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 TGRA_3 Ta Tb1 Ta Tb2 Ta TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 H'6400 H'0080 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 8.35 Example of Complementary PWM Mode Operation Rev.2.00 Sep. 27, 2007 Page 175 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initialization: In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). Set the respective initial PWM duty cycle values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 8.41 Registers and Counters Requiring Initialization Register/Counter TGRC_3 TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Set Value 1/2 PWM carrier cycle + dead time Td Dead time Td 1/2 PWM carrier cycle Initial PWM duty cycle value for each phase H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. PWM Output Level Setting: In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in the timer output control register (TOCR). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. Rev.2.00 Sep. 27, 2007 Page 176 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Dead Time Setting: In complementary PWM mode, PWM pulses are output with a nonoverlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. PWM Cycle Setting: In complementary PWM mode, the PWM pulse cycle is set in two registersTGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGRA_3 set value = TCDR set value + TDDR set value The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 8.36 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register data updating, for the method of updating the data in each buffer register. Rev.2.00 Sep. 27, 2007 Page 177 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 8.36 Example of PWM Cycle Updating Register Data Updating: In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty cycle and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 8.37 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Rev.2.00 Sep. 27, 2007 Page 178 of 448 REJ09B0394-0200 Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register : Compare register : Buffer register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H'0000 Time BR data2 data2 data3 data1 data2 data3 data4 data4 data3 data5 data5 data4 data6 data6 data6 Temp_R data1 Figure 8.37 Example of Data Update in Complementary PWM Mode 8. Multi-Function Timer Pulse Unit (MTU) Rev.2.00 Sep. 27, 2007 Page 179 of 448 REJ09B0394-0200 GR data1 8. Multi-Function Timer Pulse Unit (MTU) Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 8.38 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty cycle value is smaller than the TDDR value is shown in figure 8.39. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TGR4_A TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 8.38 Example of Initial Output in Complementary PWM Mode (1) Rev.2.00 Sep. 27, 2007 Page 180 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGR_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 8.39 Example of Initial Output in Complementary PWM Mode (2) Complementary PWM Mode PWM Output Generation Method: In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 8.40 to 8.42 show examples of waveform generation in complementary PWM mode. Rev.2.00 Sep. 27, 2007 Page 181 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a b c d (or c d a' b'), as shown in figure 8.40. If compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 8.41, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 8.42, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the positive phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. Rev.2.00 Sep. 27, 2007 Page 182 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) T2 period T1 period T1 period TGR3A_3 c TCDR d a b a' b' TDDR H'0000 Positive phase Negative phase Figure 8.40 Example of Complementary PWM Mode Waveform Output (1) T1 period TGRA_3 c TCDR a b d T2 period T1 period a b TDDR H'0000 Positive phase Negative phase Figure 8.41 Example of Complementary PWM Mode Waveform Output (2) Rev.2.00 Sep. 27, 2007 Page 183 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) T1 period TGRA_3 T2 period T1 period TCDR a b TDDR c a' H'0000 Positive phase b' d Negative phase Figure 8.42 Example of Complementary PWM Mode Waveform Output (3) T1 period TGRA_3 c d T2 period T1 period TCDR a b a' TDDR b' H'0000 Positive phase Negative phase Figure 8.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) Rev.2.00 Sep. 27, 2007 Page 184 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) T1 period TGRA_3 T2 period T1 period TCDR a b a TDDR b H'0000 Positive phase c d Negative phase Figure 8.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period TGRA_3 c d T2 period T1 period TCDR a b TDDR H'0000 Positive phase Negative phase Figure 8.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Rev.2.00 Sep. 27, 2007 Page 185 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 Positive phase Negative phase c b' d a' Figure 8.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 c ad b T2 period T1 period TCDR TDDR H'0000 Positive phase Negative phase Figure 8.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Rev.2.00 Sep. 27, 2007 Page 186 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode 0% and 100% Duty Cycle Output: In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 8.43 to 8.47 show output examples. 100% duty cycle output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty cycle output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 8.48. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 8.48 Example of Toggle Output Waveform Synchronized with PWM Output Rev.2.00 Sep. 27, 2007 Page 187 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 8.49 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNTS TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 8.49 Counter Clearing Synchronized with Another Channel Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 8.50 to 8.53 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, Rev.2.00 Sep. 27, 2007 Page 188 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 8.50 Example of Output Phase Switching by External Input (1) Rev.2.00 Sep. 27, 2007 Page 189 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 8.51 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 8.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) Rev.2.00 Sep. 27, 2007 Page 190 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 8.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3 compare-match or a compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the center of the PWM pulse. A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). Rev.2.00 Sep. 27, 2007 Page 191 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection functions. * Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller's bus control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to the mode registers, control registers, and counters. In access disabled state, an undefined value is read from the registers concerned, and cannot be modified. * Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 8.9, Port Output Enable (POE), for details. * Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. For details, see section 4.2, Function for Detecting Oscillator Halt. 8.5 8.5.1 Interrupt Sources Interrupts and Priorities There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Rev.2.00 Sep. 27, 2007 Page 192 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Table 8.42 lists the MTU interrupt sources. Table 8.42 MTU Interrupts Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TGI4C TGI4D TCI4V Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TGRC_4 input capture/compare match TGRD_4 input capture/compare match TCNT_4 overflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev.2.00 Sep. 27, 2007 Page 193 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two each for channels 1 and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one each for channels 1 and 2. 8.5.2 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match in each channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D converter at this time, A/D conversion starts. In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev.2.00 Sep. 27, 2007 Page 194 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.6 8.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 8.54 shows TCNT count timing in internal clock operation, and figure 8.55 shows TCNT count timing in external clock operation (normal mode), and figure 8.56 shows TCNT count timing in external clock operation (phase counting mode). P Falling edge Rising edge Internal clock TCNT input clock TCNT N-1 N N+1 N+2 Figure 8.54 Count Timing in Internal Clock Operation P Falling edge Rising edge Falling edge External clock TCNT input clock TCNT N-1 N N+1 N+2 Figure 8.55 Count Timing in External Clock Operation Rev.2.00 Sep. 27, 2007 Page 195 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) P External clock TCNT input clock Falling edge Rising edge Falling edge TCNT N-1 N N+1 Figure 8.56 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 8.57 shows output compare output timing (normal mode and PWM mode) and figure 8.58 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). P TCNT input clock N N+1 TCNT TGR Compare match signal TIOC pin N Figure 8.57 Output Compare Output Timing (Normal Mode/PWM Mode) Rev.2.00 Sep. 27, 2007 Page 196 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) P TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 8.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 8.59 shows input capture signal timing. P Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 8.59 Input Capture Input Signal Timing Rev.2.00 Sep. 27, 2007 Page 197 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 8.60 shows the timing when counter clearing on compare match is specified, and figure 8.61 shows the timing when counter clearing on input capture is specified. P Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 8.60 Counter Clear Timing (Compare Match) P Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 8.61 Counter Clear Timing (Input Capture) Rev.2.00 Sep. 27, 2007 Page 198 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Buffer Operation Timing: Figures 8.62 and 8.63 show the timing in buffer operation. P TCNT Compare match signal TGRA, TGRB TGRC, TGRD n n+1 n N N Figure 8.62 Buffer Operation Timing (Compare Match) P Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 8.63 Buffer Operation Timing (Input Capture) Rev.2.00 Sep. 27, 2007 Page 199 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 8.64 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. P TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 8.64 TGI Interrupt Timing (Compare Match) Rev.2.00 Sep. 27, 2007 Page 200 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TGF Flag Setting Timing in Case of Input Capture: Figure 8.65 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 8.65 TGI Interrupt Timing (Input Capture) Rev.2.00 Sep. 27, 2007 Page 201 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TCFV Flag/TCFU Flag Setting Timing: Figure 8.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 8.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. P TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 8.66 TCIV Interrupt Setting Timing P TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF TCIU interrupt Figure 8.67 TCIU Interrupt Setting Timing Rev.2.00 Sep. 27, 2007 Page 202 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 8.68 shows the timing for status flag clearing by the CPU. TSR write cycle T1 T2 P Address TSR address Write signal Status flag Interrupt request signal Figure 8.68 Timing for Status Flag Clearing by the CPU Rev.2.00 Sep. 27, 2007 Page 203 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7 8.7.1 Usage Notes Module Standby Mode Setting MTU operation can be disabled or enabled using the module standby register. The initial setting is for MTU operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 17, Power-Down Modes. 8.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.69 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev.2.00 Sep. 27, 2007 Page 204 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where P (N + 1) f : Counter frequency P : Peripheral clock operating frequency N : TGR set value Contention between TCNT Write and Clear Operations 8.7.4 If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 8.70 shows the timing in this case. TCNT write cycle T1 T2 P Address Write signal Counter clear signal TCNT TCNT address N H'0000 Figure 8.70 Contention between TCNT Write and Clear Operations Rev.2.00 Sep. 27, 2007 Page 205 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 8.71 shows the timing in this case. TCNT write cycle T2 T1 P Address TCNT address Write signal TCNT input clock TCNT N TCNT write data M Figure 8.71 Contention between TCNT Write and Increment Operations Rev.2.00 Sep. 27, 2007 Page 206 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.6 Contention between TGR Write and Compare Match When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is generated. Figure 8.72 shows the timing in this case. TGR write cycle T2 T1 P Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address Figure 8.72 Contention between TGR Write and Compare Match Rev.2.00 Sep. 27, 2007 Page 207 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write. Figures 8.73 and 8.74 show the timing in this case. TGR write cycle T1 T2 P Address Write signal Compare match signal Compare match buffer signal Buffer register TGR N M M Buffer register address Buffer register write data Figure 8.73 Contention between Buffer Register Write and Compare Match (Channel 0) Rev.2.00 Sep. 27, 2007 Page 208 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TGR write cycle T1 T2 P Address Buffer register address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M TGR N Figure 8.74 Contention between Buffer Register Write and Compare Match (Channels 3 and 4) Rev.2.00 Sep. 27, 2007 Page 209 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.8 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 8.75 shows the timing in this case. TGR read cycle T1 T2 P Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 8.75 Contention between TGR Read and Input Capture Rev.2.00 Sep. 27, 2007 Page 210 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.9 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 8.76 shows the timing in this case. TGR write cycle T1 T2 P Address Write signal Input capture signal TCNT TGR M M TGR address Figure 8.76 Contention between TGR Write and Input Capture Rev.2.00 Sep. 27, 2007 Page 211 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.10 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 8.77 shows the timing in this case. Buffer register write cycle T2 T1 P Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address Figure 8.77 Contention between Buffer Register Write and Input Capture 8.7.11 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 8.78. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Rev.2.00 Sep. 27, 2007 Page 212 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) TCNT write cycle T1 P Address Write signal TCNT_2 H'FFFE H'FFFF TCNT_2 write data TGR2A_2 to TGR2B_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D P N M M M Disabled H'FFFF N N+1 T2 TCNT_2 address Q P Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection Rev.2.00 Sep. 27, 2007 Page 213 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 8.79. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Counter operation stop Complementary PWM mode operation Complementary PMW restart Figure 8.79 Counter Value during Complementary PWM Mode Stop 8.7.13 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty cycle setting registers (TGRB_3, TRGA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4, while the TCBR functions as the TCDR's buffer register. Rev.2.00 Sep. 27, 2007 Page 214 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 8.80 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT3 Point a Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRC_3 TGRB_3, TGRA_4, TGRB_4 Point b TGRD_3, TGRC_4, TGRD_4 H'0000 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 8.80 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode Rev.2.00 Sep. 27, 2007 Page 215 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset sync PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 8.81 shows a TCFV bit operation example in reset sync PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 8.81 Reset Sync PWM Mode Overflow Flag Rev.2.00 Sep. 27, 2007 Page 216 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.16 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 8.82 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. P TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV Figure 8.82 Contention between Overflow and Counter Clearing Rev.2.00 Sep. 27, 2007 Page 217 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.17 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 8.83 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 P Address Write signal TCNT address TCNT write data TCNT H'FFFF M TCFV flag Figure 8.83 Contention between TCNT Write and Overflow 8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to registers TIOR3_H, TIOR3_L, TIOR4_H, and TIOR4_L to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronous PWM mode. Rev.2.00 Sep. 27, 2007 Page 218 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode, TIOR should be set to H'00. 8.7.20 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode. 8.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. Rev.2.00 Sep. 27, 2007 Page 219 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.8 8.8.1 MTU Output Pin Initialization Operating Modes The MTU has the following six operating modes. Waveform output is possible in all of these modes. * Normal mode (channels 0 to 4) * PWM mode 1 (channels 0 to 4) * PWM mode 2 (channels 0 to 2) * Phase counting modes 1 to 4 (channels 1 and 2) * Complementary PWM mode (channels 3 and 4) * Reset-synchronous PWM mode (channels 3 and 4) The MTU output pin initialization method for each of these modes is described in this section. 8.8.2 Reset Start Operation The MTU output pins (TIOC*) are initialized low by a reset or in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: Channel number and port notation are substituted for *. Rev.2.00 Sep. 27, 2007 Page 220 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 8.43. Table 8.43 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29) Legend: Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronous PWM mode The above abbreviations are used in some places in following descriptions. Rev.2.00 Sep. 27, 2007 Page 221 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. * When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, and then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. * When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 8.43. The active level is assumed to be low. Rev.2.00 Sep. 27, 2007 Page 222 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.84 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 8.84 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 223 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z * Not initialized (TIOC*B) Figure 8.85 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.84. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 224 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 8.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z * Not initialized (cycle register) Figure 8.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 8.84. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Rev.2.00 Sep. 27, 2007 Page 225 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 8.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after resetting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 8.87 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 8.84. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev.2.00 Sep. 27, 2007 Page 226 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 8.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (normal) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 11 12 14 15 (16) (17) (18) TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.88 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.84. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 227 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 8.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (normal) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 11 12 14 15 16 17 18 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.89 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode 1 to 13 are the same as in figure 8.88. 14. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronous PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 228 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 8.90 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z * Not initialized (TIOC*B) Figure 8.90 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 229 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.91 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z * Not initialized (TIOC*B) * Not initialized (TIOC*B) Figure 8.91 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.90. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 230 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.92 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z * Not initialized (cycle register) * Not initialized (TIOC*B) Figure 8.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 8.90. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Rev.2.00 Sep. 27, 2007 Page 231 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 8.93 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after resetting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z * Not initialized (TIOC*B) Figure 8.93 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 8.90. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev.2.00 Sep. 27, 2007 Page 232 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 8.94 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (PWM1) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 18 19 Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 * Not initialized (TIOC3B) * Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 8.94 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.90. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 233 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 8.95 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (PWM1) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 18 19 Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 * Not initialized (TIOC3B) * Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 8.95 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode 1 to 14 are the same as in figure 8.90. 15. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronous PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 234 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 8.96 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn * Not initialized (cycle register) Hi-Z Hi-Z Note: n = 0 to 15 Figure 8.96 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. 4. 5. 6. 7. 8. 9. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 235 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.97 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn * Not initialized (cycle register) * Not initialized (TIOC*B) Hi-Z Hi-Z Note: n = 0 to 15 Figure 8.97 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.96. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 236 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.98 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn * Not initialized (cycle register) * Not initialized (cycle register) Hi-Z Hi-Z Note: n = 0 to 15 Figure 8.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.96. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 237 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 8.99 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after resetting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 PFC TSTR Match Error PFC TSTR TMDR (MTU) (1) occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn * Not initialized (cycle register) Hi-Z Hi-Z Note: n = 0 to 15 Figure 8.99 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 8.96. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 238 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.100 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 8.100 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 239 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 * Not initialized (TIOC*B) Hi-Z Hi-Z Figure 8.101 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.100. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 240 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 8.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 * Not initialized (cycle register) Hi-Z Hi-Z Figure 8.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.100. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 241 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 8.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 PFC TSTR Match Error PFC TSTR TMDR (MTU) (1) occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 8.103 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 8.100. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 242 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.104 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.104 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 2. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 10. The count operation is stopped by TSTR. (MTU output becomes the complementary PWM output initial value.) 11. Set normal mode. (MTU output goes low.) 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 243 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.105 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z * Not initialized (TIOC3B) * Not initialized (TIOC3D) Figure 8.105 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.104. 11. Set PWM mode 1. (MTU output goes low.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 244 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 8.106 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty cycle settings at the time the counter was stopped). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.106 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.104. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. Rev.2.00 Sep. 27, 2007 Page 245 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 8.107 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty cycle settings). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.104. 11. Set normal mode and make new settings. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 246 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 8.108 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (RPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.108 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in figure 8.104. 11. Set normal mode. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronous PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronous PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 247 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.109 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.109 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronous PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The reset-synchronous PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU output becomes the reset-synchronous PWM output initial value.) 11. Set normal mode. (MTU positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 248 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.110 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z * Not initialized (TIOC3B) * Not initialized (TIOC3D) Figure 8.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.109. 11. Set PWM mode 1. (MTU positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 249 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 8.111 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.109. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU output with the PFC. 16. Operation is restarted by TSTR. Rev.2.00 Sep. 27, 2007 Page 250 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) (29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 8.112 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in figure 8.109. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronous PWM waveform is output on compare-match occurrence. Rev.2.00 Sep. 27, 2007 Page 251 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0 to POE3 pin input, depending on the output status of the high-current pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT). It can also simultaneously generate interrupt requests. The high-current pins also become high-impedance regardless of whether these pin functions are selected in cases such as when the oscillator stops or in standby mode. 8.9.1 Features * Each of the POE0 to POE3 input pins can be set for falling edge, P/8 x 16, P/16 x 16, or P/128 x 16 low-level sampling. * High-current pins can be set to high-impedance state by POE0 to POE3 pin falling-edge or low-level sampling. * High-current pins can be set to high-impedance state when the high-current pin output levels are compared and simultaneous low-level output continues for one cycle or more. * Interrupts can be generated by input-level sampling or output-level comparison results. Rev.2.00 Sep. 27, 2007 Page 252 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 8.113. TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Output level detection circuit Output level detection circuit Output level detection circuit OCSR Highimpedance request control signal Interrupt request (MTUPOE) ICSR1 Input level detection circuit Falling-edge detection circuit Low-level detection circuit POE3 POE2 POE1 POE0 P/8 P/16 P/128 Legend: OCSR: Output level control/status register ICSR1: Input level control/status register Figure 8.113 POE Block Diagram Rev.2.00 Sep. 27, 2007 Page 253 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.9.2 Pin Configuration Table 8.44 Pin Configuration Name Port output enable input pins Abbreviation POE0 to POE3 I/O Input Description Input request signals to make highcurrent pins high-impedance state Table 8.45 shows output-level comparisons with pin combinations. Table 8.45 Pin Combinations Pin Combination PE9/TIOC3B and PE11/TIOC3D I/O Output Description All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. PE12/TIOC4A and PE14/TIOC4C Output PE13/TIOC4B/MRES and PE15/TIOC4D/IRQOUT Output 8.9.3 Register Configuration The POE has the two registers. The input level control/status register 1 (ICSR1) controls both POE0 to POE3 pin input signal detection and interrupts. The output level control/status register (OCSR) controls both the enable/disable of output comparison and interrupts. Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1) is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Rev.2.00 Sep. 27, 2007 Page 254 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value POE3F 0 Bit 15 R/W R/(W)* Description POE3 Flag This flag indicates that a high impedance request has been input to the POE3 pin [Clearing condition] * By writing 0 to POE3F after reading a POE3F = 1 [Setting condition] * When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin 14 POE2F 0 R/(W)* POE2 Flag This flag indicates that a high impedance request has been input to the POE2 pin [Clearing condition] * By writing 0 to POE2F after reading a POE2F = 1 [Setting condition] * When the input set by ICSR1 bits 5 and 4 occurs at the POE2 pin 13 POE1F 0 R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin [Clearing condition] * By writing 0 to POE1F after reading a POE1F = 1 [Setting condition] * When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin 12 POE0F 0 R/(W)* POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin [Clearing condition] * By writing 0 to POE0F after reading a POE0F = 1 [Setting condition] * When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin Rev.2.00 Sep. 27, 2007 Page 255 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value All 0 Bit R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 9 8 PIE 0 R/W Port Interrupt Enable This bit enables/disables interrupt requests when any of the POE0F to POE3F bits of the ICSR1 are set to 1 0: Interrupt requests disabled 1: Interrupt requests enabled 7 6 POE3M1 POE3M0 0 0 R/W R/W POE3 mode 1, 0 These bits select the input mode of the POE3 pin 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE3 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE3 input has been sampled for 16 P/128 clock pulses, and all are low level. 5 4 POE2M1 POE2M0 0 0 R/W R/W POE2 mode 1, 0 These bits select the input mode of the POE2 pin 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE2 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE2 input has been sampled for 16 P/128 clock pulses, and all are low level. 3 2 POE1M1 POE1M0 0 0 R/W R/W POE1 mode 1, 0 These bits select the input mode of the POE1 pin 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE1 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE1 input has been sampled for 16 P/128 clock pulses, and all are low level. Rev.2.00 Sep. 27, 2007 Page 256 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value POE0M1 POE0M0 0 0 Bit 1 0 R/W R/W R/W Description Note: * POE0 mode 1, 0 These bits select the input mode of the POE0 pin 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE0 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE0 input has been sampled for 16 P/128 clock pulses, and all are low level. The write value should always be 0. Output Level Control/Status Register (OCSR): The output level control/status register (OCSR) is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. Bit 15 Bit Name OSF Initial value 0 R/W Description R/(W)* Output Short Flag This flag indicates that any one pair of the three pairs of 2 phase outputs compared have simultaneously become low level outputs. [Clearing condition] * By writing 0 to OSF after reading an OSF = 1 [Setting condition] * When any one pair of the three 2-phase outputs simultaneously become low level 14 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev.2.00 Sep. 27, 2007 Page 257 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 9 Bit Name OCE R/W R/W Description Output Level Compare Enable This bit enables the start of output level comparisons. When setting this bit to 1, pay attention to the output pin combinations shown in table 8.43, Mode Transition Combinations. When 0 is output, the OSF bit is set to 1 at the same time when this bit is set, and output goes to high impedance. Accordingly, bits 15 to 11 and bit 9 of the port E data register (PEDR) are set to 1. For the MTU output comparison, set the bit to 1 after setting the MTU's output pins with the PFC. Set this bit only when using pins as outputs. When the OCE bit is set to 1, if OIE = 0 a highimpedance request will not be issued even if OSF is set to 1. Therefore, in order to have a high-impedance request issued according to the result of the output level comparison, the OIE bit must be set to 1. When OCE = 1 and OIE = 1, an interrupt request will be generated at the same time as the high-impedance request: however, this interrupt can be masked by means of an interrupt controller (INTC) setting. 0: Output level compare disabled 1: Output level compare enabled; makes an output high impedance request when OSF = 1. 8 OIE 0 R/W Output Short Interrupt Enable This bit makes interrupt requests when the OSF bit of the OCSR is set. 0: Interrupt requests disabled 1: Interrupt request enabled 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * The write value should always be 0. Rev.2.00 Sep. 27, 2007 Page 258 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.9.4 Operation Input Level Detection Operation If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins become high-impedance state. However, only when the general input/output function or MTU function is selected, the large-current pin is in the high-impedance state. Falling Edge Detection: When a change from high to low level is input to the POE pins. Low-Level Detection: Figure 8.114 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR1. If even one high level is detected during this interval, the low level is not accepted. Furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection. 8/16/128 clock cycles P Sampling clock POE input PE9/ TIOC3B When low level is sampled at all points When high level is sampled at least once High-impedance state* 1 1 2 2 3 16 13 Flag set (POE received) Flag not set Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT) also go to the high-impedance state at the same timing. Figure 8.114 Low-Level Detection Operation Rev.2.00 Sep. 27, 2007 Page 259 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) Output-Level Compare Operation Figure 8.115 shows an example of the output-level compare operation for the combination of PE9/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations. P 0 level overlapping detected PE9/ TIOC3B PE11/ TIOC3D High impedance state Figure 8.115 Output-Level Detection Operation Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-current pins that have become highimpedance due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance state by clearing the OSF flag, always do so only after outputting a high level from the highcurrent pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs can be achieved by setting the MTU internal registers. Rev.2.00 Sep. 27, 2007 Page 260 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) POE Timing Figure 8.116 shows an example of timing from POE input to high impedance of pin. P CK falling POE input Falling edge detected PE9/ TIOC3B High impedance state Note: Other large-current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT) also go to the high impedance state at the same timing Figure 8.116 Falling Edge Detection Operation Rev.2.00 Sep. 27, 2007 Page 261 of 448 REJ09B0394-0200 8. Multi-Function Timer Pulse Unit (MTU) 8.9.5 Usage Note To set the POE pin as a level detection pin, a high level signal must be firstly input to the POE pin. (1) Symptom (a) Regarding the POEnF* bits If setting of the POEnF bits in the input level control/status registers (ICSR1 and ICSR2) by the 2 hardware* and reading from these bits occur simultaneously, "0" will be read, where "1" should be read. Furthermore, if clearing of these bits is attempted subsequent to the above condition, the clearing 3 should be ignored* but it will be carried out. Notes: *1 For the SH7046-Series and SH7047-Series, n = 0 to 6; for the SH7144-Series, n = 0 to 3. *2 The POEnF bits are set when the signals input to the respective POEn pins satisfy the conditions that are specified by the POEnM1 and POEnM0 of the ICSR1 and ICSR2. *3 The correct operation is that clearing of the POEnF bits is only possible after "1" is read from them in order to prevent accidental clearing. (b) Regarding the OSF bit The same symptom applies to the OSF bits of the output level control/status register (OCSR). (2) To Avoid This Problem Please clear the POEnF bits or the OSF bit in these steps: first execute a read for ICSR1, ICSR2, or OCSR, then write "0" to the bits that had a read value of "1" to clear them while writing "1" to other bits. If this procedure is not followed, the POEnF bits and the OSF bit may be cleared unexpectedly if their setting by hardware and reading occur simultaneously. 1 Rev.2.00 Sep. 27, 2007 Page 262 of 448 REJ09B0394-0200 9. Watchdog Timer Section 9 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that can reset this LSI internally if the counter overflows without rewriting the counter value due to a system crash or the like. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 9.1. 9.1 Features * Selectable from eight counter input clocks. * Switchable between watchdog timer mode and interval timer mode * Clears software standby mode In watchdog timer mode * Output WDTOVF signal * If the counter overflows, it is possible to select whether this LSI is internally reset or not. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (ITI). WDT0400A_010020030200 Rev.2.00 Sep. 27, 2007 Page 263 of 448 REJ09B0394-0200 9. Watchdog Timer Overflow ITI (interrupt request signal) Interrupt control Clock Clock select WDTOVF Internal reset signal* Reset control /2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources RSTCSR TCNT TSCR Bus interface Module bus WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by making a register setting. Power-on reset or manual reset can be selected. Figure 9.1 Block Diagram of WDT 9.2 Input/Output Pin Table 9.1 shows the pin configuration of the watchdog timer. Table 9.1 Pin Watchdog timer overflow Pin Configuration Abbreviation WDTOVF I/O O Function Outputs the counter overflow signal in watchdog timer mode Note: The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin down, a resistance of 1 M or higher should be used. Rev.2.00 Sep. 27, 2007 Page 264 of 448 REJ09B0394-0200 Internal bus 9. Watchdog Timer 9.3 Register Descriptions The WDT has the following three registers. For details, refer to section 18, List of Registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 9.6.1, Notes on Register Access. * Timer control/status register (TCSR) * Timer counter (TCNT) * Reset control/status register (RSTCSR) 9.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR. Rev.2.00 Sep. 27, 2007 Page 265 of 448 REJ09B0394-0200 9. Watchdog Timer 9.3.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* 1 Description Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag. This flag is not set in watchdog timer mode. [Setting condition] * When TCNT overflows in interval timer mode. [Clearing conditions] * * Cleared by reading OVF When 0 is written to the TME bit in interval timer mode 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. 0: Interval timer mode Interval timer interrupt (ITI) request to the CPU when TCNT overflows 1: Watchdog timer mode WDTOVF signal output externally when TCNT 2 overflows* . 5 TME 0 R/W Timer Enable Enables or disables the timer. 0: Timer disabled TCNT is initialized to H'00 and count-up stops 1: Timer enabled TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. 4, 3 All 1 R Reserved This bit is always read as 1, and should only be written with 1. Rev.2.00 Sep. 27, 2007 Page 266 of 448 REJ09B0394-0200 9. Watchdog Timer Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (). The overflow frequency for = 40 MHz is enclosed in 3 parentheses* . 000: Clock /2 (frequency: 12.8 s) 001: Clock /64 (frequency: 409.6 s) 010: Clock /128 (frequency: 0.8 ms) 011: Clock /256 (frequency: 1.6 ms) 100: Clock /512 (frequency: 3.3 ms) 101: Clock /1024 (frequency: 6.6 ms) 110: Clock /4096 (frequency: 26.2 ms) 111: Clock /8192 (frequency: 52.4 ms) Notes: 1. Only a 0 can be written after reading 1. 2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode. 3. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Rev.2.00 Sep. 27, 2007 Page 267 of 448 REJ09B0394-0200 9. Watchdog Timer 9.3.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W)* Description Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode. [Setting condition] * Set when TCNT overflows in watchdog timer mode [Clearing condition] * 6 RSTE 0 R/W Cleared by reading WOVF, and then writing 0 to WOVF Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows in watchdog timer mode. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 RSTS 0 R/W Reset Select Selects the type of internal reset generated if TCNT overflows in watchdog timer mode. 0: Power-on reset 1: Manual reset 4 to 0 All 1 R Reserved These bits are always read as 1, and should only be written with 1. Note: * Only 0 can be written, for flag clearing. Rev.2.00 Sep. 27, 2007 Page 268 of 448 REJ09B0394-0200 9. Watchdog Timer 9.4 9.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally. The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following are not initialized by a WDT reset signal: * POE (port output enable) of MTU registers * PFC (pin function controller) registers * I/O port registers These registers are initialized only by an external power-on reset. Rev.2.00 Sep. 27, 2007 Page 269 of 448 REJ09B0394-0200 9. Watchdog Timer TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written in TCNT WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WOVF = 1 Time WDTOVF signal Internal reset signal* 128 clocks 512 clocks Legend: WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 9.2 Operation in Watchdog Timer Mode Rev.2.00 Sep. 27, 2007 Page 270 of 448 REJ09B0394-0200 9. Watchdog Timer 9.4.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter (TCNT) overflows. This function can be used to generate interval timer interrupts at regular intervals. TCNT value Overflow H'FF Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI Time Legend: ITI: Interval timer interrupt request generation Figure 9.3 Operation in Interval Timer Mode 9.4.3 Clearing Software Standby Mode The watchdog timer has a special function to clear software standby mode with an NMI interrupt or IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below. Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to stop the watchdog timer counter before entering software standby mode. The chip cannot enter software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 19.3, AC Characteristics, for the oscillation settling time. Recovery from Software Standby Mode: When an NMI signal or IRQ0 to IRQ3 signals are received in software standby mode, the clock oscillator starts running and TCNT starts incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and software standby mode ends. For details on software standby mode, see section 17, Power-Down Modes. Rev.2.00 Sep. 27, 2007 Page 271 of 448 REJ09B0394-0200 9. Watchdog Timer 9.4.4 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested. Figure 9.4 shows this timing. TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 9.4 Timing of Setting OVF 9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip. Figure 9.5 shows this timing. TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 9.5 Timing of Setting WOVF Rev.2.00 Sep. 27, 2007 Page 272 of 448 REJ09B0394-0200 9. Watchdog Timer 9.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 9.2 Name ITI WDT Interrupt Source (in Interval Timer Mode) Interrupt Source TCNT overflow Interrupt Flag OVF 9.6 9.6.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 9.6). This transfers the write data from the lower byte to TCNT or TCSR. * Writing to TCNT 15 Address: H'FFFF8610 H'5A 8 7 Write data 0 * Writing to TCSR 15 Address: H'FFFF8610 H'A5 8 7 Write data 0 Figure 9.6 Writing to TCNT and TCSR Rev.2.00 Sep. 27, 2007 Page 273 of 448 REJ09B0394-0200 9. Watchdog Timer Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 9.7. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. * Writing 0 to the WOVF bit 15 Address: H'FFFF8612 H'A5 8 7 H'00 0 * Writing to the RSTE and RSTS bits 15 Address: H'FFFF8612 H'5A 8 7 Write data 0 Figure 9.7 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR, H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR. Rev.2.00 Sep. 27, 2007 Page 274 of 448 REJ09B0394-0200 9. Watchdog Timer 9.6.2 TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented. Figure 9.8 shows this operation. TCNT write cycle T1 T2 T3 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 9.8 Contention between TCNT Write and Increment 9.6.3 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0. 9.6.4 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev.2.00 Sep. 27, 2007 Page 275 of 448 REJ09B0394-0200 9. Watchdog Timer 9.6.5 System Reset by WDTOVF Signal If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 9.9. SH7101 Reset input RES Reset signal to entire system WDTOVF Figure 9.9 Example of System Reset Circuit Using WDTOVF Signal 9.6.6 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. 9.6.7 Manual Reset in Watchdog Timer Mode When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. 9.6.8 Notes on Using WDTOVF pin The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin down, a resistance of 1 M or higher should be used. Rev.2.00 Sep. 27, 2007 Page 276 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Section 10 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). 10.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source. * Choice of LSB-first or MSB-first transfer* (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. * Module standby mode can be set Asynchronous mode * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Multiprocessor bit: 1 or 0 * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCIS200B_010020030200 Rev.2.00 Sep. 27, 2007 Page 277 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Clocked Synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Note: * The description in this section are based on LSB-first transfer. Figure 10.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SSR SCR SMR SDCR Transmission/ reception control BRR P Baud rate generator P/8 P/32 P/128 Clock RxD RSR TSR TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register SDCR: Serial direction control register Figure 10.1 Block Diagram of SCI Rev.2.00 Sep. 27, 2007 Page 278 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.2 Input/Output Pins Table 10.1 shows the SCI pin configuration. Table 10.1 Pin Configuration Channel 2 Pin Name* SCK2 RxD2 TxD2 3 SCK3 RxD3 TxD3 Note: * I/O I/O Input Output I/O Input Output Function SCI2 clock input/output SCI2 receive data input SCI2 transmit data output SCI3 clock input/output SCI3 receive data input SCI3 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 10.3 Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each processing, refer to section 18, List of Registers. Channel 2 * Serial Mode Register_2 (SMR_2) * Bit Rate Register_2 (BRR_2) * Serial Control Register_2 (SCR_2) * Transmit Data Register_2 (TDR_2) * Serial Status Register_2 (SSR_2) * Receive Data Register_2 (RDR_2) * Serial Direction Control Register_2 (SDCR_2) Channel 3 * Serial Mode Register_3 (SMR_3) * Bit Rate Register_3 (BRR_3) * Serial Control Register_3 (SCR_3) * Transmit Data Register_3 (TDR_3) * Serial Status Register_3 (SSR_3) Rev.2.00 Sep. 27, 2007 Page 279 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) * Receive Data Register_3 (RDR_3) * Serial Direction Control Register_3 (SDCR_3) 10.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 10.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. The initial value of RDR is H'00. 10.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 10.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF. Rev.2.00 Sep. 27, 2007 Page 280 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. Rev.2.00 Sep. 27, 2007 Page 281 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Initial Value 0 0 Bit 1 0 Bit Name CKS1 CKS0 R/W R/W R/W Description Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/8 clock (n = 1) 10: P/32 clock (n = 2) 11: P/128 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 10.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 10.3.9, Bit Rate Register (BRR)). Rev.2.00 Sep. 27, 2007 Page 282 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 10.7, Interrupts Sources. Bit 7 6 Bit Name TIE RIE Initial Value 0 0 R/W R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 10.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable This bit is set to 1, TEI interrupt request is enabled. Rev.2.00 Sep. 27, 2007 Page 283 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Initial Value 0 0 Bit 1 0 Bit Name CKE1 CKE0 R/W R/W R/W Description Clock Enable 1 and 0 Selects the clock source and SCK pin function. Asynchronous mode: 00: Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined) 01: Internal clock, SCK pin used for clock output (The output clock frequency is the same as the bit rate) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate) 11: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate) Clocked synchronous mode: 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Rev.2.00 Sep. 27, 2007 Page 284 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * * Power-on reset or software standby mode When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Clearing condition] * 6 RDRF 0 R/(W)* When 0 is written to TDRE after reading TDRE = 1 Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * Power-on reset or software standby mode * When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 [Clearing conditions] * Power-on reset or software standby mode * When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. Rev.2.00 Sep. 27, 2007 Page 285 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Initial Value 0 Bit 4 Bit Name FER R/W R/(W)* Description Framing Error [Setting condition] * When the stop bit is 0 [Clearing conditions] * Power-on reset or software standby mode * When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. The FER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 3 PER 0 R/(W)* Parity Error [Setting condition] * When a parity error is detected during reception [Clearing conditions] * Power-on reset or software standby mode * When 0 is written to PER after reading PER = 1 The PER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2 TEND 1 R Transmit End [Setting conditions] * * * Power-on reset or software standby mode When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character [Clearing condition] * 1 MPB 0 R When 0 is written to TDRE after reading TDRE = 1 Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT sets the multiprocessor bit value to be added to the transmit data. Note: * Only 0 can be written, for flag clearing. Rev.2.00 Sep. 27, 2007 Page 286 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.3.8 Serial Direction Control Register (SDCR) The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-first transfer. Bit Bit Name Initial Value All 1 R/W R Description Reserved The write value must always be 1. Operation cannot be guaranteed if 0 is written. 3 DIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: TDR contents are transmitted in LSB-first order Receive data is stored in RDR in LSB-first 1: TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first 2 0 R Reserved The write value must always be 0. Operation cannot be guaranteed if 1 is written. 1 0 1 0 R R Reserved This bit is always read as 1, and cannot be modified. Reserved The write value must always be 0. Operation cannot be guaranteed if 1 is written. 7 to 4 10.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 10.2 shows the relationships between the N setting in BRR and the effective bit rate B0 for asynchronous and clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Rev.2.00 Sep. 27, 2007 Page 287 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0 Mode Asynchronous mode (n = 0) Asynchronous mode (n = 1 to 3) Clocked synchronous mode (n = 0) Clocked synchronous mode (n = 1 to 3) Bit Rate B0 = P x 106 32 x 2 2n Error Error (%) = B0 - 1 x 100 B 1 B0 - 1 x 100 B 1 x (N + 1) B0 = P x 106 32 x 22n+1 x (N + 1) P x 106 4 x 22n x (N + 1) P x 106 4 x 22n+1 x (N + 1) Error (%) = B0 = B0 = Notes: B0: B1: N: P: n: Effective bit rate (bit/s) Actual transfer speed according to the register settings Logical bit rate (bit/s) Specified transfer speed of the target system BRR setting for baud rate generator (0 N 255) Peripheral clock operating frequency (MHz) Determined by the SMR settings shown in the following tables. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N settings in BRR in clocked synchronous mode. For details, refer to section 10.4.2, Receive Data Sampling Timing and Reception Margin in Asynchronous Mode. Tables 10.5 and 10.7 show the maximum bit rates with external clock input. Rev.2.00 Sep. 27, 2007 Page 288 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 4 n 1 1 1 1 1 0 0 0 0 0 0 0 0 N 140 103 51 25 12 51 25 12 8 6 3 3 2 Error (%) 0.74 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -3.55 -6.99 8.51 0.00 8.51 n 1 1 1 1 0 0 0 0 0 0 0 0 0 N 212 155 77 38 155 77 38 19 12 9 6 5 4 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 -2.34 -6.99 0.00 -2.34 n 2 2 2 2 1 1 0 0 0 0 0 0 0 N 70 51 25 12 25 12 51 25 16 12 8 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 2.12 0.16 -3.55 0.00 -6.99 n 2 2 1 1 1 0 0 0 0 0 0 0 0 N 88 64 129 64 32 129 64 32 21 15 10 9 7 10 Error (%) -0.25 0.16 0.16 0.16 -1.36 0.16 0.16 -1.36 -1.36 1.73 -1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 106 77 38 77 38 155 77 38 25 19 12 11 9 12 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 0.00 -2.34 Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 14 n 2 2 2 2 1 1 0 0 0 0 0 0 0 N 123 90 45 22 45 22 90 45 29 22 14 13 10 Error (%) 0.23 0.16 -0.93 -0.93 -0.93 -0.93 0.16 -0.93 1.27 -0.93 1.27 0.00 3.57 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 141 103 51 103 51 207 103 51 34 25 16 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.79 0.16 2.12 0.00 0.16 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 159 116 58 116 58 233 116 58 38 28 19 17 14 18 Error (%) -0.12 0.16 -0.69 0.16 -0.69 0.16 0.16 -0.69 0.16 1.02 -2.34 0.00 -2.34 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 177 129 64 129 64 32 129 64 42 32 21 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 -1.36 0.16 0.16 0.94 -1.36 -1.36 0.00 1.73 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 194 142 71 142 71 35 142 71 47 35 23 21 17 22 Error (%) 0.16 0.16 -0.54 0.16 -0.54 -0.54 0.16 -0.54 -0.54 -0.54 -0.54 0.00 -0.54 Rev.2.00 Sep. 27, 2007 Page 289 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 24 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 155 77 51 38 25 23 19 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 221 162 80 162 80 40 162 80 53 40 26 24 19 25 Error (%) -0.02 -0.15 0.47 -0.15 0.47 -0.76 -0.15 0.47 0.47 -0.76 0.47 0.00 1.73 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 230 168 84 168 84 41 168 84 55 41 27 25 20 26 Error (%) -0.08 0.16 -0.43 0.16 -0.43 0.76 0.16 -0.43 0.76 0.76 0.76 0.00 0.76 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 248 181 90 181 90 45 181 90 60 45 29 27 22 28 Error (%) -0.17 0.16 0.16 0.16 0.16 -0.93 0.16 0.16 -0.39 -0.93 1.27 0.00 -0.93 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 66 194 97 48 97 48 194 97 64 48 32 29 23 30 Error (%) -0.62 0.16 -0.35 -0.35 -0.35 -0.35 0.16 -0.35 0.16 -0.35 -1.36 0.00 1.73 Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 32 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 70 207 103 51 103 51 207 103 68 51 34 31 25 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.64 0.16 -0.79 0.00 0.16 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 74 220 110 54 110 51 220 110 73 54 36 33 27 34 Error (%) 0.62 0.16 -0.29 0.62 -0.29 6.42 0.16 -0.29 -0.29 0.62 -0.29 0.00 -1.18 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 79 233 116 58 116 58 234 116 77 58 38 35 28 36 Error (%) -0.12 0.16 0.16 -0.69 0.16 -0.69 -0.27 0.16 0.16 -0.69 0.16 0.00 1.02 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 83 246 123 61 123 61 246 123 81 61 40 37 30 38 Error (%) 0.40 0.16 -0.24 -0.24 -0.24 -0.24 0.16 -0.24 0.57 -0.24 0.57 0.00 -0.24 n 3 3 2 2 1 1 1 0 0 0 0 0 0 N 88 64 129 64 129 64 32 129 86 64 42 39 32 40 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 0.16 -0.22 0.16 0.94 0.00 -1.36 Rev.2.00 Sep. 27, 2007 Page 290 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode) P (MHz) 4 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Maximum Bit Rate (bit/s) 125000 250000 312500 375000 437500 500000 562500 625000 687500 750000 781250 812500 875000 937500 1000000 1062500 1125000 1187500 1250000 Rev.2.00 Sep. 27, 2007 Page 291 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P (MHz) 4 6 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 External Clock (MHz) 1.0000 1.5000 2.0000 2.5000 3.0000 3.5000 4.0000 4.5000 5.0000 5.5000 6.0000 6.2500 6.5000 7.0000 7.5000 8.0000 8.5000 9.0000 9.5000 10.0000 Maximum Bit Rate (bit/s) 62500 93750 125000 156250 187500 218750 250000 281250 312500 343750 375000 390625 406250 437500 468750 500000 531250 562500 593750 625000 Rev.2.00 Sep. 27, 2007 Page 292 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 4 n 2 1 1 1 1 0 0 0 0 0 0 0 N 124 249 124 49 24 99 39 19 9 3 1 0 n 2 1 1 0 0 0 0 0 0 6 N 187 187 74 149 59 29 14 5 2 n 2 2 1 1 1 1 1 1 0 0 0 0 8 N 249 124 249 99 49 24 9 4 19 7 3 1 n 2 1 0 0 0 0 0 0 0 10 N 155 124 249 99 49 24 9 4 0 n 2 1 1 1 0 0 0 0 0 12 N 187 149 74 14 59 29 11 5 2 Operating Frequency P (MHz) Logical Bit Rate (bit/s) 14 n N n 16 N n 18 N n 20 N n 22 N 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 3 2 2 1 0 0 0 0 0 108 218 108 174 139 69 34 13 6 3 2 2 2 2 1 1 1 1 1 1 0 124 249 124 49 24 49 19 9 4 1 0 3 3 2 1 1 0 0 0 0 0 140 140 224 112 179 89 44 17 8 3 2 1 1 1 0 0 0 0 0 0 0 155 155 249 124 24 99 49 19 9 4 1 0 3 3 1 0 0 0 0 0 171 42 137 219 109 54 21 10 Rev.2.00 Sep. 27, 2007 Page 293 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 24 n 3 2 2 1 1 1 1 0 0 0 0 N 187 187 74 149 74 29 14 59 23 11 5 n 3 2 1 0 0 0 25 N 194 194 155 249 124 24 n 3 3 2 1 0 0 0 0 26 N 202 101 202 162 129 64 25 12 n 3 3 2 1 1 0 0 0 0 0 28 N 218 108 218 174 34 139 69 27 13 6 n 3 3 2 1 0 0 0 0 0 30 N 233 116 233 187 149 74 29 14 2 Operating Frequency P (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 32 n 3 3 2 2 2 2 2 2 1 1 1 1 N 249 124 249 99 49 24 9 4 9 3 1 0 n 3 2 1 1 0 0 0 0 34 N 132 105 212 105 169 84 33 16 n 3 2 1 1 1 0 0 0 0 0 36 N 140 112 224 112 44 179 89 35 17 8 n 3 2 1 1 0 0 0 0 38 N 147 118 237 118 189 94 37 18 n 3 2 1 1 1 1 0 0 0 0 0 0 40 N 155 124 249 124 49 24 99 39 19 9 3 1 Rev.2.00 Sep. 27, 2007 Page 294 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) P (MHz) 4 6 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 External Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 3.6667 4.0000 4.1667 4.3333 4.6667 5.0000 5.3333 5.6667 6.0000 6.3333 6.6667 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 3666666.7 4000000.0 4166666.7 4333333.3 4666666.7 5000000.0 5333333.3 5666666.7 6000000.0 6333333.3 6666666.7 Legend: : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. Note: Settings with an error of 1% or less are recommended. Rev.2.00 Sep. 27, 2007 Page 295 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.4 Operation in Asynchronous Mode Figure 10.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Idle state (mark state) 1 LSB 0 Start bit 1 bit D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Serial data Transmit/receive data 7 or 8 bits Stop bit 1 or 2 bits One unit of transfer data (character or frame) Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 10.4.1 Data Transfer Format Table 10.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 10.5, Multiprocessor Communication Function. Rev.2.00 Sep. 27, 2007 Page 296 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 11 12 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 X 1 0 S 8-bit data MPB STOP 0 X 1 1 S 8-bit data MPB STOP STOP 1 X 1 0 S 7-bit data MPB STOP 1 X 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit X: Don't care Rev.2.00 Sep. 27, 2007 Page 297 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.3. Thus the reception margin in asynchronous mode is given by formula (1) below. M= 0.5 - (D - 0.5) 1 - - (L - 0.5) F N 2N x 100% ........................... Formula (1) Where M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode Rev.2.00 Sep. 27, 2007 Page 298 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.4. The clock must not be stopped during operation. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 10.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev.2.00 Sep. 27, 2007 Page 299 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start transmission [1] Set the clock selection in SCR. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external colck is used. [4] Set the RIE, TIE, TEIE, and MPIE bits. [5] Set PFC of the external pin used. Set RxD input during receiving and TxD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. [6] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1.* At this time, the TxD, RxD, and SCK pins can be used. The TxD pin is in a mark state during transmitting, and RxD pin is in an idle state for waiting the start bit during receiving. Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCR to 0* Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Set data transfer format in SMR Set value in BRR Wait [1] [2] [3] No 1-bit interval elapsed? Yes Set the RIE, TIE, TEIE, and MPIE bits in SCR Set PFC of the external pin used SCK, TxD, RxD Set TE and RE bits of SCR to 1 [4] [5] [6] < Initialization completion> Note: * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 10.5 Sample SCI Initialization Flowchart Rev.2.00 Sep. 27, 2007 Page 300 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.4.5 Data Transmission (Asynchronous Mode) Figure 10.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 10.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 TxD 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.2.00 Sep. 27, 2007 Page 301 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [1] SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: No To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to select the TxD pin as an output port. [4] Initialization Start transmission [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Break output? Yes Clear DR to 0 No Clear TE bit in SCR to 0; select the TxD pin as an output port with the PFC Figure 10.7 Sample Serial Transmission Flowchart Rev.2.00 Sep. 27, 2007 Page 302 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.4.6 Serial Data Reception (Asynchronous Mode) Figure 10.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 RxD 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ERI interrupt request generated by framing error 1 frame Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev.2.00 Sep. 27, 2007 Page 303 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Table 10.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.9 shows a sample flow chart for serial data reception. Table 10.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains its state before data reception. Rev.2.00 Sep. 27, 2007 Page 304 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [1] SCI initialization: Set the RxD pin using the PFC. Initialization Start reception [1] [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to Read ORER, PER, and [2] identify the error. After performing the FER flags in SSR appropriate error processing, ensure that the ORER, PER, and FER flags are Yes all cleared to 0. Reception cannot be PER FER ORER = 1 resumed if any of these flags are set to [3] 1. In the case of a framing error, a No Error processing break can be detected by reading the value of the input port corresponding to (Continued on next page) the RxD pin. Read RDRF flag in SSR No [4] [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. [5] RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 10.9 Sample Serial Reception Data Flowchart (1) Rev.2.00 Sep. 27, 2007 Page 305 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 10.9 Sample Serial Reception Data Flowchart (2) Rev.2.00 Sep. 27, 2007 Page 306 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 10.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev.2.00 Sep. 27, 2007 Page 307 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev.2.00 Sep. 27, 2007 Page 308 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.5.1 Multiprocessor Serial Data Transmission Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission Read TDRE flag in SSR No [2] [1] [1] SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to select the TxD pin as an output port. [4] TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 No No Clear TE bit in SCR to 0; select the TxD pin as an output port with the PFC Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart Rev.2.00 Sep. 27, 2007 Page 309 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.5.2 Multiprocessor Serial Data Reception Figure 10.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 10.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 Data (ID1) MPB D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0 1 RxD 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated ID1 RDR data read If not this station's ID, and RDRF flag MPIE bit is set to 1 cleared to 0 in again RXI interrupt processing routine RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 RxD Start bit 0 D0 Data (ID2) D1 D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Data2 Matches this station's ID, MPIE bit is set to 1 so reception continues, again and data is received in RXI interrupt processing routine (b) Data matches station's ID Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.2.00 Sep. 27, 2007 Page 310 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [1] SCI initialization: Set the RxD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4] No Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No [1] Yes [3] RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR Yes RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev.2.00 Sep. 27, 2007 Page 311 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes Clear ORER and FER flags in SSR to 0 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.2.00 Sep. 27, 2007 Page 312 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.6 Operation in Clocked Synchronous Mode Figure 10.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. Data is transferred in 8-bit units. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) 10.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the clock is fixed high. Rev.2.00 Sep. 27, 2007 Page 313 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 10.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or the contents of RDR. Start initialization [1] Set the clock selection in SCR. [2] Set the data transfer format in SMR. Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCR to 0* Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Set data transfer format in SMR Set value in BRR Wait No [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Set the RIE, TIE TEIE, and MPIE bits. [1] [5] Set PFC of the external pin used. Set RxD input during receiving and TxD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. [6] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1.* At this time, the TxD, RxD, and SCK pins can be used. The TxD pin is in a mark state during transmitting. When synchronous clock output (clock master) is set during receiving in synchronous mode, outputting clocks from the SCK pin starts. [2] [3] 1-bit interval elapsed? Yes Set the RIE, TIE, TEIE, and MPIE bits in SCR Set PFC of the external pin used SCK, TxD, RxD Set TE and RE bits of SCR to 1 [4] [5] [6] Figure 10.15 Sample SCI Initialization Flowchart Rev.2.00 Sep. 27, 2007 Page 314 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 10.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI) interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 10.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev.2.00 Sep. 27, 2007 Page 315 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 0 Bit 4 Bit 5 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev.2.00 Sep. 27, 2007 Page 316 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [1] SCI initialization: Set the TxD pin using the PFC. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [3] Initialization Start transmission [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 No Figure 10.17 Sample Serial Transmission Flowchart Rev.2.00 Sep. 27, 2007 Page 317 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 10.18 Example of SCI Operation in Reception Rev.2.00 Sep. 27, 2007 Page 318 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.19 shows a sample flowchart for serial data reception. [1] SCI initialization: Set the RxD pin using the PFC. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. Initialization Start reception [1] Read ORER flag in SSR Yes [2] ORER = 1 No [3] No [4] SCI status check and receive data read: Error processing Read SSR and check that the RDRF flag is set to 1, then read the receive (Continued below) data in RDR and clear the RDRF flag Read RDRF flag in SSR [4] to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. [5] No All data received? Yes Clear RE bit in SCR to 0 [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 10.19 Sample Serial Reception Flowchart Rev.2.00 Sep. 27, 2007 Page 319 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI initialization. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev.2.00 Sep. 27, 2007 Page 320 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) [1] SCI initialization: Set the TxD and RxD pins using the PFC. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Initialization Start transmission/reception [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR Yes [3] Error processing [4] ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear TE and RE bits in SCR to 0 [5] Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.2.00 Sep. 27, 2007 Page 321 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.7 10.7.1 Interrupts Sources Interrupts in Normal Serial Communication Interface Mode Table 10.10 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 10.10 SCI Interrupt Sources Channel 2 Name ERI_2 RXI_2 TXI_2 TEI_2 3 ERI_3 RXI_3 TXI_3 TEI_3 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND Rev.2.00 Sep. 27, 2007 Page 322 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.8 10.8.1 Usage Notes TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating transferring of transmit data from TDR into TSR. The SCI sets the TDRE bit to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that the TDRE bit is set to 1. 10.8.2 Module Standby Mode Setting SCI operation can be disabled or enabled using the module standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 17, Power-Down Modes. 10.8.3 Break Detection and Processing (Asynchronous Mode Only) When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 10.8.4 Sending a Break Signal (Asynchronous Mode Only) The TxD pin becomes of the I/O port general I/O pin with the I/O direction and level determined by the port data register (DR) and the port I/O register (IOR) of the pin function controller (PFC). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When the TE bit is cleared to 0, the transmission section is initialized regardless of the present transmission status. Rev.2.00 Sep. 27, 2007 Page 323 of 448 REJ09B0394-0200 10. Serial Communication Interface (SCI) 10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 10.8.6 Cautions on Clocked Synchronous External Clock Mode 1. Set TE = RE = 1 only when external clock SCK is 1. 2. Do not set TE = RE = 1 until at least four P clocks after external clock SCK has changed from 0 to 1. 3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5-3.5 P clocks from the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. 10.8.7 Caution on Clocked Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 P clocks from the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. Rev.2.00 Sep. 27, 2007 Page 324 of 448 REJ09B0394-0200 11. A/D Converter Section 11 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter. The block diagram of the A/D converter is shown in figure 11.1. 11.1 Features * 10-bit resolution * Input channels 8 channels (two independent A/D conversion modules) * Conversion time: 6.7 s per channel (at P = 20-MHz operation) 5.4 s per channel (at P = 25-MHz operation) * Three operating modes Single mode: Single-channel A/D conversion Continuous scan mode: 1 to 4 channels Single-cycle scan mode: 1 to 4 channels * Data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three methods for conversion start Software Conversion start trigger from multifunction timer pulse unit (MTU) External trigger signal * Interrupt source An A/D conversion end interrupt request (ADI) can be generated * Module standby mode can be set ADCMS20B_010020030200 Rev.2.00 Sep. 27, 2007 Page 325 of 448 REJ09B0394-0200 11. A/D Converter Module data bus Bus interface ADDR15 ADCSR ADDR8 ADTSR ADCR * * * Internal data bus AVCC 10-bit D/A AVSS Successive approximations register + AN8 * P/4 P/8 Comparator Multiplexer Control circuit * * * * * P/16 P/32 Sample-andhold circuit AN15 ADI interrupt signal Conversion start trigger from MTU ADTRG Legend: ADCR: A/D control register ADCSR: A/D control/status register ADTSR: A/D trigger select register ADDR8-ADDR15: A/D data register 8 to 15 Note: The register number corresponds to the channel number of the module. Figure 11.1 Block Diagram of A/D Converter (For One Module) Rev.2.00 Sep. 27, 2007 Page 326 of 448 REJ09B0394-0200 11. A/D Converter 11.2 Input/Output Pins Table 11.1 summarizes the input pins used by the A/D converter. This LSI has two A/D conversion modules, each of which can be operated independently. The input channels are divided into four channel sets. Table 11.1 Pin Configuration Module Type Common Pin Name AVCC AVSS ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply and reference voltage Analog block ground and reference voltage A/D external trigger input pin Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 Group 1 Group 1 A/D module 0 (A/D0) AN8 AN9 AN10 AN11 A/D module 1 (A/D1) AN12 AN13 AN14 AN15 Note: The connected A/D module differs for each pin. The control registers of each module must be set. Rev.2.00 Sep. 27, 2007 Page 327 of 448 REJ09B0394-0200 11. A/D Converter 11.3 Register Descriptions The A/D converter has the following registers. For details on register addresses and register states in each operating mode, refer to section 18, List of Registers. * A/D data register 8 (H/L) (ADDR8) * A/D data register 9 (H/L) (ADDR9) * A/D data register 10 (H/L) (ADDR10) * A/D data register 11 (H/L) (ADDR11) * A/D data register 12 (H/L) (ADDR12) * A/D data register 13 (H/L) (ADDR13) * A/D data register 14 (H/L) (ADDR14) * A/D data register 15 (H/L) (ADDR15) * A/D control/status register_0 (ADCSR_0) * A/D control/status register_1 (ADCSR_1) * A/D control register_0 (ADCR_0) * A/D control register_1 (ADCR_1) * A/D trigger select register (ADTSR) 11.3.1 A/D Data Registers 8 to 15 (ADDR8 to ADDR15) ADDR are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. (For example, the conversion result of AN8 is stored in ADDR8.) The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading ADDR, read only the upper byte, or read in word unit. ADDR are initialized to H'0000. Rev.2.00 Sep. 27, 2007 Page 328 of 448 REJ09B0394-0200 11. A/D Converter 11.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) ADCSR for each module controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode [Clearing condition] * 6 ADIE 0 R/W When 0 is written after reading ADF = 1 A/D Interrupt Enable The A/D conversion end interrupt (ADI) request is enabled when 1 is set. When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCR) to 0. 5 4 ADM1 ADM0 0 0 R/W R/W A/D Mode 1 and 0 Select the A/D conversion mode. 00: Single mode 01: 4-channel scan mode 10: Setting prohibited 11: Setting prohibited When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCR) to 0. 3 1 R Reserved This bit is always read as 1. The write value should always be 1. 2 1 0 Note: * CH2 CH1 CH0 0 0 0 R/W R/W R/W Channel Select 2 to 0 Select analog input channels. See table 11.2. When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCR) to 0. Only 0 can be written to clear the flag. Rev.2.00 Sep. 27, 2007 Page 329 of 448 REJ09B0394-0200 11. A/D Converter Table 11.2 Channel Select List Analog Input Channels Bit 2 CH2 1 Bit 1 CH1 0 Bit 0 CH0 0 1 1 Note: * 0 1 A/D0 AN8 AN9 AN10 AN11 Single Mode A/D1 AN12 AN13 AN14 AN15 A/D0 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 4-Channel Scan Mode* A/D1 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 Continuous scan mode or single-cycle scan mode can be selected with the ADCS bit. 11.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ADCR for each module controls A/D conversion started by an external trigger signal and selects the operating clock. Bit 7 Bit Name TRGE Initial Value 0 R/W R/W Description Trigger Enable Enables or disables triggering of A/D conversion by ADTRG or an MTU trigger. 0: A/D conversion triggering is disabled 1: A/D conversion triggering is enabled 6 5 CKS1 CKS0 0 0 R/W R/W Clock Select 0 and 1 Select the A/D conversion time. 00: P/32 01: P/16 10: P/8 11: P/4 When changing the A/D conversion time, first clear the ADST bit in the A/D control registers (ADCR) to 0. CKS [1,0] = b'11 can be set while P 25 MHz. Rev.2.00 Sep. 27, 2007 Page 330 of 448 REJ09B0394-0200 11. A/D Converter Initial Value 0 Bit 4 Bit Name ADST R/W R/W Description A/D Start Starts or stops A/D conversion. When this bit is set to 1, A/D conversion is started. When this bit is cleared to 0, A/D conversion is stopped and the A/D converter enters the idle state. In single or single-cycle scan mode, this bit is automatically cleared to 0 when A/D conversion ends on the selected single channel. In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode, or module standby mode. 3 ADCS 0 R/W A/D Continuous Scan Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. 0: Single-cycle scan 1: Continuous scan When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCR) to 0. 2 to 0 All 1 R Reserved These bits are always read as 1. The write value should always be 1. Rev.2.00 Sep. 27, 2007 Page 331 of 448 REJ09B0394-0200 11. A/D Converter 11.3.4 A/D Trigger Select Register (ADTSR) ADTSR enables an A/D conversion started by an external trigger signal. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 2 TRG1S1 TRG1S0 0 0 R/W R/W AD Trigger 1 Select 1 and 0 Enable the start of A/D conversion by A/D1 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: Setting prohibited When changing the operating mode, first clear the TRGE and ADST bits in the A/D control registers (ADCR) to 0. 1 0 TRG0S1 TRG0S0 0 0 R/W R/W AD Trigger 0 Select 1 and 0 Enable the start of A/D conversion by A/D0 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: Setting prohibited When changing the operating mode, first clear the TRGE and ADST bits in the A/D control registers (ADCR) to 0. 7 to 4 Rev.2.00 Sep. 27, 2007 Page 332 of 448 REJ09B0394-0200 11. A/D Converter 11.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. The ADST bit can be set at the same time when the operating mode or analog input channel is changed. 11.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. 11.4.2 Continuous Scan Mode In continuous scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). The operations are as follows. 1. When the ADST bit in ADCR is set to 1 by software, MTU, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. Rev.2.00 Sep. 27, 2007 Page 333 of 448 REJ09B0394-0200 A/D continuous conversion Set*1 Clear*1 11. A/D Converter ADST Clear*1 ADF A/D conversion time Conversion standby Conversion standby A/D conversion (4) A/D conversion (1) Conversion standby Channel 8 (AN8) Operation condition Conversion standby Conversion standby A/D conversion (2) A/D conversion (3) Rev.2.00 Sep. 27, 2007 Page 334 of 448 REJ09B0394-0200 A/D 2 conversion (5) * Conversion standby Conversion standby Conversion standby Transfer A/D conversion result (1) A/D conversion result (4) A/D conversion result (2) A/D conversion result (3) Channel 9 (AN9) Operation condition Channel 10 (AN10) Operation condition Channel 11 (AN11) Operation condition ADDR8 ADDR9 ADDR10 ADDR11 Figure 11.2 Operation Example in Continuous Scan Mode (Three Channels Selected) (AN8 to AN10) Notes: 1. indicates command execution by the software 2. Data is ignored during conversion 11. A/D Converter 11.4.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (four channels maximum). Operations are as follows. 1. When the ADST bit in ADCR is set to 1 by a software, MTU, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. 11.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCR is set to 1, then starts conversion. Figure 11.3 shows the A/D conversion timing. Table 11.3 shows the A/D conversion time. As indicated in figure 11.3, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total conversion time therefore varies within the ranges indicated in table 11.3. In scan mode, the values given in table 11.3 apply to the first conversion time. The values given in table 11.4 apply to the second and subsequent conversions. Rev.2.00 Sep. 27, 2007 Page 335 of 448 REJ09B0394-0200 11. A/D Converter A/D conversion time (tCONV) Analog input A/D conversion start sampling time(tSPL) delay time(tD) Write cycle A/D synchronization time (Up to (3 states) 59 states) P Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle state Sample-and-hold A/D conversion ADF End of A/D conversion Figure 11.3 A/D Conversion Timing Table 11.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 31 Typ 256 Max 62 1055 Min 15 515 CKS0 = 1 Typ 128 Max 30 530 Min 7 259 CKS0 = 0 Typ 64 Max 14 266 Min 3 131 CKS1 = 1 CKS0 = 1 Typ 32 Max 6 134 1024 Note: All values represent the number of states for P. Rev.2.00 Sep. 27, 2007 Page 336 of 448 REJ09B0394-0200 11. A/D Converter Table 11.4 A/D Conversion Time (Scan Mode) CKS1 0 1 CKS0 0 1 0 1 Conversion Time (State) 1024 (Fixed) 512 (Fixed) 256 (Fixed) 128 (Fixed) 11.4.5 A/D Converter Activation by MTU The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU. To activate the A/D converter by the MTU, set the A/D trigger select register (ADTSR). When the TRGS1 and TRGS0 bits in ADTSR are set to 00 or 01, if an A/D conversion request from the interval timer of the MTU occurs, the ADST bit in ADCR is automatically set to 1. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 11.4.6 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 00 or 01 in ADTSR, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 11.4 shows the timing. CK ADTRG External trigger signal ADST A/D conversion Figure 11.4 External Trigger Input Timing Rev.2.00 Sep. 27, 2007 Page 337 of 448 REJ09B0394-0200 11. A/D Converter 11.5 Interrupt Sources The A/D converter generates an A/D conversion end interrupt (ADI) upon the completion of A/D conversion. ADI interrupt requests are enabled when the ADIE bit is set to 1 while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. Table 11.5 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion completed Interrupt Source Flag ADF 11.6 Definitions of A/D Conversion Accuracy This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 11.5). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 11.6). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 11.6). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 11.6). * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev.2.00 Sep. 27, 2007 Page 338 of 448 REJ09B0394-0200 11. A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 11.5 Definitions of A/D Conversion Accuracy Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 11.6 Definitions of A/D Conversion Accuracy Rev.2.00 Sep. 27, 2007 Page 339 of 448 REJ09B0394-0200 11. A/D Converter 11.7 11.7.1 Usage Notes Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the module standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 17, Power-Down Modes. 11.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less, or 3 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k or 3 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 11.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 11.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). This LSI Sensor output impedance of up to 3 k or up to 1 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 11.7 Example of Analog Input Circuit Rev.2.00 Sep. 27, 2007 Page 340 of 448 REJ09B0394-0200 11. A/D Converter 11.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 11.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN8 to AN15), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 11.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN8 to AN15), between AVcc and AVss, as shown in figure 11.8. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN8 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN8 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. Rev.2.00 Sep. 27, 2007 Page 341 of 448 REJ09B0394-0200 11. A/D Converter AVCC Rin*2 *1 0.1 F 100 AN8 to AN15 AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 11.8 Example of Analog Input Protection Circuit Table 11.6 Analog Pin Specifications Item Analog input capacitance Min Max 20 3 1 Unit pF k k p 20 MHz 20 MHz < P 25 MHz Measurement Condition Permissible signal source impedance 10 k AN8 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 11.9 Analog Input Pin Equivalent Circuit Rev.2.00 Sep. 27, 2007 Page 342 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) Section 12 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 12.1 Features * Four types of counter input clock can be selected One of four internal clocks (P/8, P/32, P/128, P/512) can be selected independently for each channel. * Interrupt sources A compare match interrupt can be requested independently for each channel. * Module standby mode can be set Figure 12.1 shows a block diagram of the CMT. CMI0 P/32 P/512 P/8 P/128 CMI1 P/32 P/512 P/8 P/128 Control circuit Clock selection Control circuit Clock selection Comparator CMCOR0 CMCSR0 CMCOR1 CMCSR1 CMCNT0 Comparator CMCNT1 CMSTR Module bus CMT Legend: CMSTR: CMCSR: CMCOR: CMCNT: CMI: Bus interface Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 12.1 CMT Block Diagram TIMCMT0A_010020030200 Rev.2.00 Sep. 27, 2007 Page 343 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.2 Register Descriptions The CMT has the following registers. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Compare Match Timer Start Register (CMSTR) * Compare Match Timer Control/Status Register_0 (CMCSR_0) * Compare Match Timer Counter_0 (CMCNT_0) * Compare Match Timer Constant Register_0 (CMCOR_0) * Compare Match Timer Control/Status Register_1 (CMCSR_1) * Compare Match Timer Counter_1 (CMCNT_1) * Compare Match Timer Constant Register_1 (CMCOR_1) 12.2.1 Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 This bit selects whether to operate or halt compare match timer counter_1. 0: CMCNT_1 count operation halted 1: CMCNT_1 count operation 0 STR0 0 R/W Count Start 0 This bit selects whether to operate or halt compare match timer counter_0. 0: CMCNT_0 count operation halted 1: CMCNT_0 count operation 15 to 2 Rev.2.00 Sep. 27, 2007 Page 344 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.2.2 Compare Match Timer Control/Status Register_0 and _1 (CMCSR_0, CMCSR_1) CMCSR is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag This flag indicates whether or not the CMCNT and CMCOR values have matched. 0: CMCNT and CMCOR values have not matched [Clearing condition] * Write 0 to CMF after reading 1 from it 1: CMCNT and CMCOR values have matched 6 CMIE 0 R/W Compare Match Interrupt Enable This bit selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W These bits select the clock input to CMCNT among the four internal clocks obtained by dividing the peripheral clock (P). When the STR bit in CMSTR is set to 1, CMCNT begins incrementing with the clock selected by CKS1 and CKS0. 00: P/8 01: P/32 10: P/128 11: P/512 Note: * Only 0 can be written, for flag clearing. 15 to 8 Rev.2.00 Sep. 27, 2007 Page 345 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.2.3 Compare Match Timer Counter_0 and _1 (CMCNT_0, CMCNT_1) CMCNT is a 16-bit register used as an up-counter for generating interrupt requests. CMCNT is initialized to H'0000. 12.2.4 Compare Match Timer Constant Register_0 and _1 (CMCOR_0, CMCOR_1) CMCOR is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is initialized to H'FFFF. 12.3 12.3.1 Operation Cyclic Count Operation When an internal clock is selected with the CKS1, CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag in CMCSR is set to 1. If the CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 12.2 shows the compare match counter operation. CMCNT value Counter cleared by CMCOR compare match CMCOR H'0000 Time Figure 12.2 Counter Operation Rev.2.00 Sep. 27, 2007 Page 346 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.3.2 CMCNT Count Timing One of four internal clocks (P/8, P/32, P/128, P/512) obtained by dividing the peripheral clock (P) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing. P Internal clock CMCNT input clock CMCNT N-1 N N+1 Figure 12.3 Count Timing 12.4 12.4.1 Interrupts Interrupt Sources The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for details. 12.4.2 Compare Match Flag Set Timing The CMF bit in CMCSR is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 12.4 shows the CMF bit set timing. Rev.2.00 Sep. 27, 2007 Page 347 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) P CMCNT input clock CMCNT CMCOR Compare match signal CMF CMI N N 0 Figure 12.4 CMF Set Timing 12.4.3 Compare Match Flag Clear Timing The CMF bit in CMCSR is cleared by writing 0 to it after reading 1. Figure 12.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 P CMF Figure 12.5 Timing of CMF Clear by CPU Rev.2.00 Sep. 27, 2007 Page 348 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.5 12.5.1 Usage Notes Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 12.6 shows the timing. CMCNT write cycle T1 T2 P Address Internal write signal Compare match signal CMCNT N H'0000 CMCNT Figure 12.6 CMCNT Write and Compare Match Contention Rev.2.00 Sep. 27, 2007 Page 349 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 12.7 shows the timing. CMCNT write cycle T1 T2 P Address Internal write signal CMCNT input clock CMCNT N M CMCNT write data CMCNT Figure 12.7 CMCNT Word Write and Increment Contention Rev.2.00 Sep. 27, 2007 Page 350 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) 12.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 12.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 T2 P Address Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X CMCNTH Figure 12.8 CMCNT Byte Write and Increment Contention Rev.2.00 Sep. 27, 2007 Page 351 of 448 REJ09B0394-0200 12. Compare Match Timer (CMT) Rev.2.00 Sep. 27, 2007 Page 352 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Section 13 Pin Function Controller (PFC) The pin function controller (PFC) is composed of those registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 13.1 to 13.5 list the multiplexed pins of this LSI. Tables 13.6 lists the pin functions in each operating mode. Table 13.1 Multiplexed Pins (Port A) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 (Related (Related (Related (Related (Related (Related Port Module) Module) Module) Module) Module) Module) A PA0 I/O (port) PA1 I/O (port) PA2 I/O (port) PA3 I/O (port) PA4 I/O (port) PA5 I/O (port) PA6 I/O (port) PA7 I/O (port) PA8 I/O (port) PA9 I/O (port) PA10 I/O (port) PA11 I/O (port) PA12 I/O (port) PA13 I/O (port) IRQ0 input (INTC) IRQ1 input (INTC) Function 7 (Related Module) Function 8 (Related Module) POE0 input RXD2 input (port) (SCI) POE1 input TXD2 output (port) (SCI) SCK2 I/O (SCI) RXD3 input (SCI) TXD3 output (SCI) SCK3 I/O (SCI) TCLKA input (MTU) TCLKB input (MTU) TCLKC input (MTU) TCLKD input (MTU) ADTRG input (A/D) RXD2 input (SCI) TXD2 output (SCI) RXD3 input (SCI) TXD3 output (SCI) SCK2 I/O (SCI) SCK3 I/O (SCI) Rev.2.00 Sep. 27, 2007 Page 353 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 (Related (Related (Related (Related (Related (Related Port Module) Module) Module) Module) Module) Module) A PA14 I/O (port) PA15 I/O (port) Function 7 (Related Module) Function 8 (Related Module) Table 13.2 Multiplexed Pins (Port B) Port B Function 1 (Related Module) PB2 I/O (port) PB3 I/O (port) PB4 I/O (port) PB5 I/O (port) Function 2 (Related Module) IRQ0 input (INTC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) Function 3 (Related Module) POE0 input (port) POE1 input (port) POE2 input (port) POE3 input (port) Function 4 (Related Module) Rev.2.00 Sep. 27, 2007 Page 354 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Table 13.3 Multiplexed Pins (Port E) Port E Function 1 (Related Module) PE0 I/O (port) PE1 I/O (port) PE2 I/O (port) PE3 I/O (port) PE4 I/O (port) PE5 I/O (port) PE6 I/O (port) PE7 I/O (port) PE8 I/O (port) PE9 I/O (port) PE10 I/O (port) PE11 I/O (port) PE12 I/O (port) PE13 I/O (port) PE14 I/O (port) PE15 I/O (port) PE16 I/O (port) PE17 I/O (port) PE18 I/O (port) PE19 I/O (port) PE20 I/O (port) PE21 I/O (port) Function 2 (Related Module) TIOC0A I/O (MTU) TIOC0B I/O (MTU) TIOC0C I/O (MTU) TIOC0D I/O (MTU) TIOC1A I/O (MTU) TIOC1B I/O (MTU) TIOC2A I/O (MTU) TIOC2B I/O (MTU) TIOC3A I/O (MTU) TIOC3B I/O (MTU) TIOC3C I/O (MTU) TIOC3D I/O (MTU) TIOC4A I/O (MTU) TIOC4B I/O (MTU) TIOC4C I/O (MTU) TIOC4D I/O (MTU) Function 3 (Related Module) RXD3 input (SCI) TXD3 output (SCI) SCK3 I/O (SCI) MRES input (INTC) Function 4 (Related Module) IRQOUT output (INTC) Rev.2.00 Sep. 27, 2007 Page 355 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Table 13.4 Multiplexed Pins (Port F) Port F Function 1 (Related Module) PF8 input (port) PF9 input (port) PF10 input (port) PF11 input (port) PF12 input (port) PF13 input (port) PF14 input (port) PF15 input (port) Function 2 (Related Module) AN8 input (A/D0) AN9 input (A/D0) AN10 input (A/D0) AN11 input (A/D0) AN12 input (A/D1) AN13 input (A/D1) AN14 input (A/D1) AN15 input (A/D1) Function 3 (Related Module) Function 4 (Related Module) Table 13.5 Multiplexed Pins (Port G) Port G Function 1 (Related Module) PG0 input (port) PG1 input (port) PG2 input (port) PG3 input (port) Rev.2.00 Sep. 27, 2007 Page 356 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Table 13.6 Pin Functions in Each Operating Mode Pin Name Single Chip Mode Pin No. 11, 43, 66 9, 24, 41, 64 22, 62 27, 38 25, 40 1 2 3 4 5 6 7 8 10 12 13 14 15 16 17 18 19 20 21 23 26 28 29 30 31 Initial Function Vcc Vss VCL AVcc AVss PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PG3 PFC Selected Function Possibilities Vcc Vss VCL AVcc AVss PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RxD3 PE5/TIOC1B/TxD3 PE6/TIOC2A/SCK3 PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16 PE17 PE18 PE19 PE20 PE21 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PG3 Rev.2.00 Sep. 27, 2007 Page 357 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Pin Name Single Chip Mode Pin No. 32 33 34 35 36 37 39 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 63 65 67 68 69 Initial Function PG2 PG1 PG0 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PB5 PB4 PB3 PB2 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FWP RES NMI MD3 PFC Selected Function Possibilities PG2 PG1 PG0 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PB3/IRQ1/POE1 PB2/IRQ0/POE0 PA15 PA14 PA13 PA12 PA11/ADTRG/SCK3 PA10/SCK2 PA9/TCLKD/TXD3 PA8/TCLKC/RXD3 PA7/TCLKB/TXD2 PA6/TCLKA/RXD2 PA5/IRQ1/SCK3 PA4/TXD3 PA3/RXD3 PA2/IRQ0/SCK2 PA1/POE1/TXD2 PA0/POE0/RXD2 FWP RES NMI MD3 Rev.2.00 Sep. 27, 2007 Page 358 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Pin Name Single Chip Mode Pin No. 70 71 72 73 74 75 76 77 78 79 80 Initial Function MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0 PE1 PFC Selected Function Possibilities MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B Note: In single chip mode, do not set functions other than those that can be set by PFC listed in this table. Rev.2.00 Sep. 27, 2007 Page 359 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) 13.1 Register Descriptions The PFC has the following registers. For details on the addresses of the registers and their states during each process, see section 18, List of Registers. * Port A I/O register L (PAIORL) * Port A control register L3 (PACRL3) * Port A control register L2 (PACRL2) * Port A control register L1 (PACRL1) * Port B I/O register (PBIOR) * Port B control register 1 (PBCR1) * Port B control register 2 (PBCR2) * Port E I/O register H (PEIORH) * Port E I/O register L (PEIORL) * Port E control register H (PECRH) * Port E control register L1 (PECRL1) * Port E control register L2 (PECRL2) 13.1.1 Port A I/O Register L (PAIORL) PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0), and SCK2 and SCK3 pins are functioning as inputs/outputs of SCI. In other states, PAIORL is disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an input pin if the bit is cleared to 0. PAIORL is initialized to H'0000. Rev.2.00 Sep. 27, 2007 Page 360 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) 13.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1) PACRL3 to PACRL1 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port A. Port A Control Registers L3 to L1 (PACRL3 to PACRL1) Register PACRL3 PACRL1 PACRL1 Bit 15 15 14 Bit Name PA15MD2 PA15MD1 PA15MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA15 Mode Select the function of the PA15 pin. 000: PA15 I/O (port) 001: Setting prohibited 010: Setting prohibited PACRL3 PACRL1 PACRL1 14 13 12 PA14MD2 PA14MD1 PA14MD0 0 0 0 R/W R/W R/W PA14 Mode Select the function of the PA14 pin. 000: PA14 I/O (port) 001: Setting prohibited 010: Setting prohibited PACRL3 PACRL1 PACRL1 13 11 10 PA13MD2 PA13MD1 PA13MD0 0 0 0 R/W R/W R/W PA13 Mode Select the function of the PA13 pin. 000: PA13 I/O (port) 001: Setting prohibited 010: Setting prohibited PACRL3 PACRL1 PACRL1 12 9 8 PA12MD2 PA12MD1 PA12MD0 0 0 0 R/W R/W R/W PA12 Mode Select the function of the PA12 pin. 000: PA12 I/O (port) 001: Setting prohibited 010: Setting prohibited PACRL3 PACRL1 PACRL1 11 7 6 PA11MD2 PA11MD1 PA11MD0 0 0 0 R/W R/W R/W PA11 Mode Select the function of the PA11/ADTRG/SCK3 pin. 000: PA11 I/O (port) 001: Setting prohibited 010: ADTRG input (A/D) 011: Setting prohibited 100: Setting prohibited 101: SCK3 I/O (SCI) 110: Setting prohibited 111: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited Rev.2.00 Sep. 27, 2007 Page 361 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Initial Value 0 0 0 Register PACRL3 PACRL1 PACRL1 Bit 10 5 4 Bit Name PA10MD2 PA10MD1 PA10MD0 R/W R/W R/W R/W Description PA10 Mode Select the function of the PA10/SCK2 pin. 000: PA10 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: SCK2 I/O (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 9 3 2 PA9MD2 PA9MD1 PA9MD0 0 0 0 R/W R/W R/W PA9 Mode Select the function of the PA9/TCLKD/TXD3 pin. 000: PA9 I/O (port) 001: TCLKD input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: TXD3 output (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 8 1 0 PA8MD2 PA8MD1 PA8MD0 0 0 0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/RXD3 pin. 000: PA8 I/O (port) 001: TCLKC input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: RXD3 input (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 7 15 14 PA7MD2 PA7MD1 PA7MD0 0 0 0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/TXD2 pin. 000: PA7 I/O (port) 001: TCLKB input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: TXD2 output (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 6 13 12 PA6MD2 PA6MD1 PA6MD0 0 0 0 R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA/RXD2 pin. 000: PA6 I/O (port) 001: TCLKA input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: RXD2 input (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 5 11 10 PA5MD2 PA5MD1 PA5MD0 0 0 0 R/W R/W R/W PA5 Mode Select the function of the PA5/IRQ1/SCK3 pin. 000: PA5 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ1 input (INTC) 100: Setting prohibited 101: Setting prohibited 110: SCK3 I/O (SCI) 111: Setting prohibited Rev.2.00 Sep. 27, 2007 Page 362 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Initial Value 0 0 0 Register PACRL3 PACRL2 PACRL2 Bit 4 9 8 Bit Name PA4MD2 PA4MD1 PA4MD0 R/W R/W R/W R/W Description PA4 Mode Select the function of the PA4/TXD3 pin. 000: PA4 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: TXD3 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 3 7 6 PA3MD2 PA3MD1 PA3MD0 0 0 0 R/W R/W R/W PA3 Mode Select the function of the PA3/RXD3 pin. 000: PA3 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: RXD3 input (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 2 5 4 PA2MD2 PA2MD1 PA2MD0 0 0 0 R/W R/W R/W PA2 Mode Select the function of the PA2/IRQ0/SCK2 pin. 000: PA2 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ0 input (INTC) 100: Setting prohibited 101: Setting prohibited 110: SCK2 I/O (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 1 3 2 PA1MD2 PA1MD1 PA1MD0 0 0 0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TXD2 pin. 000: PA1 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE1 input (port) 110: TXD2 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 0 1 0 PA0MD2 PA0MD1 PA0MD0 0 0 0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RXD2 pin. 000: PA0 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE0 input (port) 110: RXD2 input (SCI) 111: Setting prohibited Note: x means "don't care". Rev.2.00 Sep. 27, 2007 Page 363 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) 13.1.3 Port B I/O Register (PBIOR) PBIOR is a 16-bit readable/writable register that is used to set the pins on port B as inputs or outputs. Bits PB5IOR to PB2IOR correspond to pins PB5 to PB2 (names of multiplexed pins are here given as port names and pin numbers alone). PBIOR is enabled when port B pins are functioning as general-purpose inputs/outputs (PB5 to PB2). In other states, PBIOR is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 6, 1, and 0 are reserved. These bits are always read as 0. The write value should always be 0. PBIOR is initialized to H'0000. Rev.2.00 Sep. 27, 2007 Page 364 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) 13.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port B. Port B Control Registers 1 and 2 (PBCR1 and PBCR2) Register PBCR1 PBCR1 PBCR2 PBCR2 PBCR1 PBCR2 PBCR2 Bit 15, 14 9 to 0 15 to 12 3 to 0 13 11 10 Bit Name PB5MD2 PB5MD1 PB5MD0 Initial Value All 0 All 0 All 0 All 0 0 0 0 R/W R R R R R/W R/W R/W PB5 Mode Select the function of the PB5/IRQ3/POE3 pin. 000: PB5 I/O (port) 010: POE3 input (port) PBCR1 PBCR2 PBCR2 12 9 8 PB4MD2 PB4MD1 PB4MD0 0 0 0 R/W R/W R/W PB4 Mode Select the function of the PB4/IRQ2/POE2 pin. 000: PB4 I/O (port) 010: POE2 input (port) PBCR1 PBCR2 PBCR2 11 7 6 PB3MD2 PB3MD1 PB3MD0 0 0 0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1 pin. 000: PB3 I/O (port) 010: POE1 input (port) PBCR1 PBCR2 PBCR2 10 5 4 PB2MD2 PB2MD1 PB2MD0 0 0 0 R/W R/W R/W PB2 Mode Select the function of the PB2/IRQ0/POE0 pin. 000: PB2 I/O (port) 010: POE0 input (port) 011: Setting prohibited 001: IRQ0 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ1 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ2 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ3 input (INTC) 1xx: Setting prohibited Description Reserved These bits are always read as 0. The write value should always be 0. Note: x means "don't care". Rev.2.00 Sep. 27, 2007 Page 365 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) 13.1.5 Port E I/O Registers L and H (PEIORL and PEIORH) PEIORL and PEIORH are 16-bit readable/writable registers that are used to set the pins on port E as inputs or outputs. Bits PE21IOR to PE0IOR correspond to pins PE21 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PE0), TIOC pins are functioning as inputs/outputs of MTU, and SCK3 pins are functioning as inputs/outputs of SCI. In other states, PEIORL is disabled. PEIORH is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE21 to PE16). In other states, PEIORH is disabled. A given pin on port E will be an output pin if the corresponding PEIORL or PEIORH bit is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 6 in PEIORH are reserved. These bits are always read as 0. The write value should always be 0. PEIORL and PEIORH are initialized to H'0000. 13.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) PECRL1, PECRL2 and PECRH are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port E. Rev.2.00 Sep. 27, 2007 Page 366 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) Register PECRH Bit 15 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. PECRH PECRH 11 10 PE21MD1 PE21MD0 0 0 R/W R/W PE21 Mode Select the function of the PE21 pin. 00: PE21 I/O (port) 01: Setting prohibited PECRH PECRH 9 8 PE20MD1 PE20MD0 0 0 R/W R/W PE20 Mode Select the function of the PE20 pin. 00: PE20 I/O (port) 01: Setting prohibited PECRH PECRH 7 6 PE19MD1 PE19MD0 0 0 R/W R/W PE19 Mode Select the function of the PE19 pin. 00: PE19 I/O (port) 01: Setting prohibited PECRH PECRH 5 4 PE18MD1 PE18MD0 0 0 R/W R/W PE18 Mode Select the function of the PE18 pin. 00: PE18 I/O (port) 01: Setting prohibited PECRH PECRH 3 2 PE17MD1 PE17MD0 0 0 R/W R/W PE17 Mode Select the function of the PE17 pin. 00: PE17 I/O (port) 01: Setting prohibited PECRH PECRH 1 0 PE16MD1 PE16MD0 0 0 R/W R/W PE16 Mode Select the function of the PE16 pin. 00: PE16 I/O (port) 01: Setting prohibited PECRL1 PECRL1 15 14 PE15MD1 PE15MD0 0 0 R/W R/W PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 00: PE15 I/O (port) 01: TIOC4D I/O (MTU) 10: Setting prohibited 11: IRQOUT output (INTC) 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited Rev.2.00 Sep. 27, 2007 Page 367 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Initial Value 0 0 Register PECRL1 PECRL1 Bit 13 12 Bit Name PE14MD1 PE14MD0 R/W R/W R/W Description PE14 Mode Select the function of the PE14/TIOC4C pin. 00: PE14 I/O (port) 01: TIOC4C I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 11 10 PE13MD1 PE13MD0 0 0 R/W R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU) 10: MRES input (INTC) 11: Setting prohibited PECRL1 PECRL1 9 8 PE12MD1 PE12MD0 0 0 R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 00: PE12 I/O (port) 01: TIOC4A I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 7 6 PE11MD1 PE11MD0 0 0 R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 00: PE11 I/O (port) 01: TIOC3D I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 5 4 PE10MD1 PE10MD0 0 0 R/W R/W PE10 Mode Select the function of the PE10/TIOC3C pin. 00: PE10 I/O (port) 01: TIOC3C I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 3 2 PE9MD1 PE9MD0 0 0 R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 00: PE9 I/O (port) 01: TIOC3B I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 1 0 PE8MD1 PE8MD0 0 0 R/W R/W PE8 Mode Select the function of the PE8/TIOC3A pin. 00: PE8 I/O (port) 01: TIOC3A I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 15 14 PE7MD1 PE7MD0 0 0 R/W R/W PE7 Mode Select the function of the PE7/TIOC2B pin. 00: PE7 I/O (port) 01: TIOC2B I/O (MTU) 10: Setting prohibited 11: Setting prohibited Rev.2.00 Sep. 27, 2007 Page 368 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) Initial Value 0 0 Register PECRL2 PECRL2 Bit 13 12 Bit Name PE6MD1 PE6MD0 R/W R/W R/W Description PE6 Mode Select the function of the PE6/TIOC2A/SCK3 pin. 00: PE6 I/O (port) 01: TIOC2A I/O (MTU) 10: SCK3 I/O (SCI) 11: Setting prohibited PECRL2 PECRL2 11 10 PE5MD1 PE5MD0 0 0 R/W R/W PE5 Mode Select the function of the PE5/TIOC1B/TXD3 pin. 00: PE5 I/O (port) 01: TIOC1B I/O (MTU) 10: TXD3 output (SCI) 11: Setting prohibited PECRL2 PECRL2 9 8 PE4MD1 PE4MD0 0 0 R/W R/W PE4 Mode Select the function of the PE4/TIOC1A/RXD3 pin. 00: PE4 I/O (port) 01: TIOC1A I/O (MTU) 10: RXD3 input (SCI) 11: Setting prohibited PECRL2 PECRL2 7 6 PE3MD1 PE3MD0 0 0 R/W R/W PE3 Mode Select the function of the PE3/TIOC0D pin. 00: PE3 I/O (port) 01: TIOC0D I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 5 4 PE2MD1 PE2MD0 0 0 R/W R/W PE2 Mode Select the function of the PE2/TIOC0C pin. 00: PE2 I/O (port) 01: TIOC0C I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 3 2 PE1MD1 PE1MD0 0 0 R/W R/W PE1 Mode Select the function of the PE1/TIOC0B pin. 00: PE1 I/O (port) 01: TIOC0B I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 1 0 PE0MD1 PE0MD0 0 0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU) 10: Setting prohibited 11: Setting prohibited Rev.2.00 Sep. 27, 2007 Page 369 of 448 REJ09B0394-0200 13. Pin Function Controller (PFC) 13.2 13.2.1 Usage Notes Note on PFC Setting In this LSI, individual functions are available as multiplexed functions on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. When the pin function controller (PFC) is used to select a function, only a single pin can be specified for each function. If one function is specified for two or more pins, the function will not work properly. 13.2.2 Note on PFC Setting Order When a pin function is selected, the port I/O registers (PAIORL and PBIORL) must be set after setting the port control registers (PACRL3, PACRL2, PACRL1, PBCR2, and PBCR1. When a pin function which is multiplexed with the port E is selected, do not care about the setting order of the port control registers (PECRH, PECRL1, and PECRL2) and the port I/O registers (PEIORH and PEIORL). Rev.2.00 Sep. 27, 2007 Page 370 of 448 REJ09B0394-0200 14. I/O Ports Section 14 I/O Ports This LSI has five ports: A, B, E, F, and G. Port A is a 16-bit port, port B is a 4-bit port, and port E is a 22-bit port, all supporting both input and output. Port F is an 8-bit port and port G is a 4-bit port, both for input-only. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. 14.1 Port A Port A is an input/output port with the 16 pins shown in figure 14.1. PA15 to PA12 have an input-pull up MOS. PA15 (I/O) PA14 (I/O) PA13 (I/O) PA12 (I/O) PA11 (I/O) / ADTRG (input) / SCK3 (I/O) PA10 (I/O) / SCK2 (I/O) PA9 (I/O) / TCLKD (input) / TXD3 (output) Port A PA8 (I/O) / TCLKC (input) / RXD3 (input) PA7 (I/O) / TCLKB (input) / TXD2 (output) PA6 (I/O) / TCLKA (input) / RXD2 (input) PA5 (I/O) / IRQ1 (input) / SCK3 (I/O) PA4 (I/O) / TXD3 (output) PA3 (I/O) / RXD3 (input) PA2 (I/O) / IRQ0 (input) / SCK2 (I/O) PA1 (I/O) / POE1 (input) / TXD2 (output) PA0 (I/O) / POE0 (input) / RXD2 (input) Figure 14.1 Port A Rev.2.00 Sep. 27, 2007 Page 371 of 448 REJ09B0394-0200 14. I/O Ports 14.1.1 Register Description Port A is a 16-bit input/output port. Port A has the following register. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Port A data register L (PADRL) 14.1.2 Port A Data Register L (PADRL) PADRL is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRL, although that value is written into PADRL, it does not affect the pin state. Table 14.1 summarizes port A data register L read/write operations. Rev.2.00 Sep. 27, 2007 Page 372 of 448 REJ09B0394-0200 14. I/O Ports Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 14.1 Table 14.1 Port A Data Register L (PADRL) Read/Write Operations Bits 15 to 0: PAIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADRL value PADRL value Write Can write to PADRL, but it has no effect on pin state Can write to PADRL, but it has no effect on pin state Value written is output from pin Can write to PADRL, but it has no effect on pin state Rev.2.00 Sep. 27, 2007 Page 373 of 448 REJ09B0394-0200 14. I/O Ports 14.2 Port B Port B is an input/output port with the four pins shown in figure 14.2. PB5 (I/O) / IRQ3 (input) / POE3 (input) Port B PB4 (I/O) / IRQ2 (input) / POE2 (input) PB3 (I/O) / IRQ1 (input) / POE1 (input) PB2 (I/O) / IRQ0 (input) / POE0 (input) Figure 14.2 Port B 14.2.1 Register Description Port B is a 4-bit input/output port. Port B has the following register. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Port B data register (PBDR) 14.2.2 Port B Data Register (PBDR) PBDR is a 16-bit readable/writable register that stores port B data. Bits PB5DR to PB2DR correspond to pins PB5 to PB2 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PBDR is read, the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR, it does not affect the pin state. Table 14.2 summarizes port B data register read/write operations. Rev.2.00 Sep. 27, 2007 Page 374 of 448 REJ09B0394-0200 14. I/O Ports Initial Value All 0 Bit Bit Name R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 6 5 4 3 2 1, 0 PB5DR PB4DR PB3DR PB2DR 0 0 0 0 All 0 R/W R/W R/W R/W R See table 14.2 Reserved These bits are always read as 0. The write value should always be 0. Table 14.2 Port B Data Register (PBDR) Read/Write Operations Bits 5 to 2: PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Can write to PBDR, but it has no effect on pin state Can write to PBDR, but it has no effect on pin state Value written is output from pin Can write to PBDR, but it has no effect on pin state Rev.2.00 Sep. 27, 2007 Page 375 of 448 REJ09B0394-0200 14. I/O Ports 14.3 Port E Port E is an input/output port with the 22 pins shown in figure 14.3. PE21 to PE16 have an input-pull up MOS. PE21 (I/O) PE20 (I/O) PE19 (I/O) PE18 (I/O) PE17 (I/O) PE16 (I/O) PE15 (I/O) / TIOC4D (I/O) / IRQOUT (output) PE14 (I/O) / TIOC4C (I/O) PE13 (I/O) / TIOC4B (I/O) / MRES (input) Port E PE12 (I/O) / TIOC4A (I/O) PE11 (I/O) / TIOC3D (I/O) PE10 (I/O) / TIOC3C (I/O) PE9 (I/O) / TIOC3B (I/O) PE8 (I/O) / TIOC3A (I/O) PE7 (I/O) / TIOC2B (I/O) PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O) PE5 (I/O) / TIOC1B (I/O) / TXD3 (output) PE4 (I/O) / TIOC1A (I/O) / RXD3 (input) PE3 (I/O) / TIOC0D (I/O) PE2 (I/O) / TIOC0C (I/O) PE1 (I/O) / TIOC0B (I/O) PE0 (I/O) / TIOC0A (I/O) Figure 14.3 Port E Rev.2.00 Sep. 27, 2007 Page 376 of 448 REJ09B0394-0200 14. I/O Ports 14.3.1 Register Descriptions Port E has the following registers. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Port E data register H (PEDRH) * Port E data register L (PEDRL) 14.3.2 Port E Data Registers H and L (PEDRH and PEDRL) PEDRH and PEDRL are 16-bit readable/writable registers that store port E data. Bits PE21DR to PE0DR correspond to pins PE21 to PE0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PEDRH or PEDRL, that value is output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PEDRH or PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is written into PEDRH or PEDRL it does not affect the pin state. Table 14.3 summarizes port E data register read/write operations. PEDRH: Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 PE21DR PE20DR PE19DR PE18DR PE17DR PE16DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W See table 14.3. 15 to 6 Rev.2.00 Sep. 27, 2007 Page 377 of 448 REJ09B0394-0200 14. I/O Ports PEDRL: Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 14.3. Table 14.3 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations Bits 5 to 0 in PEDRH and bits 15 to 0 in PEDRL: PEIOR 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state PEDRH or PEDRL value Write Can write to PEDRH or PEDRL, but it has no effect on pin state Can write to PEDRH or PEDRL, but it has no effect on pin state Value written is output from pin (POE pin = high)* High impedance regardless of PEDRH or PEDRL value (POE pin = low)* Can write to PEDRH or PEDRL, but it has no effect on pin state Other than general output Note: * PEDRH or PEDRL value Control by the POE pin is only available for large current-output pins (PE9 and PE11 to PE15). Rev.2.00 Sep. 27, 2007 Page 378 of 448 REJ09B0394-0200 14. I/O Ports 14.4 Port F Port F is an input-only port with the eight pins shown in figure 14.4. PF15 (input) / AN15 (input) PF14 (input) / AN14 (input) PF13 (input) / AN13 (input) Port F PF12 (input) / AN12 (input) PF11 (input) / AN11 (input) PF10 (input) / AN10 (input) PF9 (input) / AN9 (input) PF8 (input) / AN8 (input) Figure 14.4 Port F 14.4.1 Register Description Port F is an 8-bit input-only port. Port F has the following register. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Port F data register (PFDR) 14.4.2 Port F Data Register (PFDR) PFDR is a 16-bit read-only register that stores port F data. Bits PF15DR to PF8DR correspond to pins PF15 to PF8 (multiplexed functions omitted here). Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read out. Table 14.4 summarizes port F data register read operation. Rev.2.00 Sep. 27, 2007 Page 379 of 448 REJ09B0394-0200 14. I/O Ports Bit 15 14 13 12 11 10 9 8 Bit Name PF15DR PF14DR PF13DR PF12DR PF11DR PF10DR PF9DR PF8DR Initial Value 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* All 0 R/W R R R R R R R R R Reserved These bits are always read as 0. Note: * Initial values are dependent on the state of the external pins. Description See table 14.4. 7 to 0 Table 14.4 Port F Data Register (PFDR) Read/Write Operations Bits 15 to 8: Pin Function General input ANn input Read Pin state 1 Write Ignored (no effect on pin state) Ignored (no effect on pin state) Rev.2.00 Sep. 27, 2007 Page 380 of 448 REJ09B0394-0200 14. I/O Ports 14.5 Port G Port G is an input-only port with the four pins shown in figure 14.5. PG3 (input) PG2 (input) Port G PG1 (input) PG0 (input) Figure 14.5 Port G 14.5.1 Register Description Port G is a 4-bit input-only port. Port G has the following register. For details on register addresses and register states during each processing, refer to section 18, List of Registers. * Port G data register (PGDR) 14.5.2 Port G Data Register (PGDR) PGDR is an 8-bit read-only register that stores port G data. Bits PG3DR to PG0DR correspond to pins PG3 to PG0. Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. Table 14.5 summarizes port G data register read operation. Bit 7 to 4 3 2 1 0 Note: * Bit Name PG3DR PG2DR PG1DR PG0DR Initial Value All 0 0/1* 0/1* 0/1* 0/1* R/W R R R R R Description Reserved These bits are always read as 0. See table 14.5. Initial values are dependent on the state of the external pins. Rev.2.00 Sep. 27, 2007 Page 381 of 448 REJ09B0394-0200 14. I/O Ports Table 14.5 Port G Data Register (PGDR) Read/Write Operations Bits 3 to 0: Pin Function General input Read Pin state Write Ignored (no effect on pin state) Rev.2.00 Sep. 27, 2007 Page 382 of 448 REJ09B0394-0200 15. Mask ROM Section 15 Mask ROM This LSI is available with 32 kbytes of on-chip mask ROM. The on-chip ROM is connected to the CPU through a 32-bit data bus (figure 15.1). The CPU can access the on-chip ROM in 8, 16 and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle. Internal data bus (32 bits) H'00000000 H'00000004 H'00000001 H'00000005 H'00000002 H'00000006 H'00000003 H'00000007 On-chip ROM H'00007FFC H'00007FFD H'00007FFE H'00007FFF Figure 15.1 Mask ROM Block Diagram The on-chip ROM is allocated to addresses H'00000000 to H'00007FFF. 15.1 Usage Note * Setting module standby mode For mask ROM, this module can be disabled/enabled by the module standby control register. Mask ROM operation is enabled for the initial value. Accessing mask ROM is disabled by setting module standby mode. For details, see section 17, Power-Down Modes. Rev.2.00 Sep. 27, 2007 Page 383 of 448 REJ09B0394-0200 15. Mask ROM Rev.2.00 Sep. 27, 2007 Page 384 of 448 REJ09B0394-0200 16. RAM Section 16 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the onchip RAM can always be accessed in one cycle, providing high-speed access that makes this RAM ideal for use as a program area, stack area, or data area. The contents of the on-chip RAM are retained in both sleep and standby modes. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), refer to section 17.2.2, System Control Register (SYSCR). Product Type SH7101 Type of ROM Mask ROM RAM Capacity 2 kbytes RAM Address H'FFFFF800 to H'FFFFFFFF 16.1 Usage Note * Module Standby Mode Setting RAM can be enabled/disabled by the module standby control register. The initial value enables RAM operation. RAM access is disabled by setting the module standby mode. For details, see section 17, Power-Down Modes. RAM0200A_000020030200 Rev.2.00 Sep. 27, 2007 Page 385 of 448 REJ09B0394-0200 16. RAM Rev.2.00 Sep. 27, 2007 Page 386 of 448 REJ09B0394-0200 17. Power-Down Modes Section 17 Power-Down Modes In addition to the normal program execution state, this LSI has three power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral functions, and so on. This LSI's power-down modes are as follows: (1) Sleep mode (2) Software standby mode (3) Module standby mode Sleep mode indicates the state of the CPU, and module standby mode indicates the state of the onchip peripheral function. Some of these states can be combined. After a reset, the LSI is in normal-operation mode. Table 17.1 lists internal operation states in each mode. LPWSH20A_010020030200 Rev.2.00 Sep. 27, 2007 Page 387 of 448 REJ09B0394-0200 17. Power-Down Modes Table 17.1 Internal Operation States in Each Mode Function System clock pulse generator CPU Instructions Registers External interrupts Peripheral functions NMI IRQ3 to IRQ0 I/O port WDT SCI A/D MTU CMT ROM RAM Functioning Functioning Retained Retained Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted (reset) Retained Halted (retained) Halted (reset) Functioning Functioning Functioning Functioning Normal operation Functioning Functioning Sleep Functioning Module Standby Software Standby Functioning Halted Halted (retained) Halted (retained) Functioning Notes: 1. "Halted (retained)" means that the operation of the internal state is suspended, although internal register values are retained. 2. "Halted (reset)" means that internal register values and internal state are initialized. 3. In module standby mode, only modules for which a stop setting has been made are halted (reset or retained). 4. There are two types of on-chip peripheral module registers; ones which are initialized in software standby mode and module standby mode, and those not initialized those modes. For details, refer to section 18.3, Register States in Each Operating Mode. 5. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port in software standby mode. For details on the setting, refer to section 17.2.1, Standby Control Register (SBYCR). For the state of pins, refer to appendix A, Pin States. Rev.2.00 Sep. 27, 2007 Page 388 of 448 REJ09B0394-0200 17. Power-Down Modes Reset state Program-halted state RES pin = High Program execution state SLEEP instruction SSBY = 0 Sleep mode (main clock) Normal-operation mode (main clock) SLEEP instruction External interrupt * SSBY = 1 Software standby mode : Transition after exception processing Notes: * : Power-down mode NMI and IRQ * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * In any state, a transition to the reset state occurs when RES is driven low. Figure 17.1 Mode Transition Diagram 17.1 Input/Output Pins Table 17.2 lists the pins relating to power-down mode. Table 17.2 Pin Configuration Pin Name RES MRES I/O Input Input Function Power-on reset input pin Manual reset input pin Rev.2.00 Sep. 27, 2007 Page 389 of 448 REJ09B0394-0200 17. Power-Down Modes 17.2 Register Descriptions Registers related to power down modes are shown below. For details on register addresses and register states during each process, refer to section 18, List of Registers. * Standby control register (SBYCR) * System control register (SYSCR) * Module standby control register 1 (MSTCR1) * Module standby control register 2 (MSTCR2) 17.2.1 Standby Control Register (SBYCR) SBYCR is an 8-bit readable/writable register that performs software standby mode control. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit specifies the transition mode after executing the SLEEP instruction. 0: Shifts to sleep mode after the SLEEP instruction has been executed 1: Shifts to software standby mode after the SLEEP instruction has been executed This bit cannot be set to 1 when the watchdog timer (WDT) is operating (when the TME bit in TCSR of the WDT is set to 1). When transferring to software standby mode, clear the TME bit to 0, stop the WDT, then set the SSBY bit to 1. 6 HIZ 0 R/W Port High-Impedance In software standby mode, this bit selects whether the pin state of the I/O port is retained or changed to highimpedance. 0: In software standby mode, the pin state is retained. 1: In software standby mode, the pin state is changed to high-impedance. The HIZ bit cannot be set to 1 when the TME bit in TCSR of the WDT is set to 1. When changing the pin state of the I/O port to highimpedance, clear the TME bit to 0, then set the HIZ bit to 1. Rev.2.00 Sep. 27, 2007 Page 390 of 448 REJ09B0394-0200 17. Power-Down Modes Initial Value 0 Bit 5 Bit Name R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 4 to 1 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 0 IRQEL 1 R/W IRQ3 to IRQ0 Enable IRQ interrupts are enabled to clear software standby mode. 0: Software standby mode is cleared. 1: Software standby mode is not cleared. Rev.2.00 Sep. 27, 2007 Page 391 of 448 REJ09B0394-0200 17. Power-Down Modes 17.2.2 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM. Bit 7, 6 Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RAME 1 R/W RAM Enable This bit enables/disables the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled When this bit is cleared to 0, the access to the on-chip RAM is disabled. In this case, an undefined value is returned when reading or fetching the data or instruction from the onchip RAM, and writing to the on-chip RAM is ignored. When RAME is cleared to 0 to disable the on-chip RAM, an instruction to access the on-chip RAM should not be set next to the instruction to write to SYSCR. If such an instruction is set, normal access is not guaranteed. When RAME is set to 1 to enable the on-chip RAM, an instruction to read SYSCR should be set next to the instruction to write to SYSCR. If an instruction to access the on-chip RAM is set next to the instruction to write to SYSCR, normal access is not guaranteed. Rev.2.00 Sep. 27, 2007 Page 392 of 448 REJ09B0394-0200 17. Power-Down Modes 17.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2) MSTCR, comprising two 16-bit readable/writable registers, performs module standby mode control. Setting a bit to 1, the corresponding module enters module standby mode, while clearing the bit to 0 clears the module standby mode. MSTCR1 Bit Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 11 10 9, 8 MSTP27 MSTP26 0 0 All 0 R/W R/W R On-chip RAM On-chip ROM Reserved These bits are always read as 0. The write value should always be 0. 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 1 R Reserved This bit is always read as 1. The write value should always be 1. 4 1 R Reserved This bit is always read as 1. The write value should always be 1. 3 2 1, 0 MSTP19 MSTP18 1 1 All 1 R/W R/W R Serial communication interface 3 (SCI_3) Serial communication interface 2 (SCI_2) Reserved These bits are always read as 1. The write value should always be 1. 15 to 12 Rev.2.00 Sep. 27, 2007 Page 393 of 448 REJ09B0394-0200 17. Power-Down Modes MSTCR2 Bit 15 Bit Name Initial Value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. 14 1 R Reserved This bit is always read as 1. The write value should always be 1. 13 12 MSTP13 MSTP12 1 1 All 0 R/W R/W R Multi-function timer pulse unit (MTU) Compare match timer (CMT) Reserved These bits are always read as 0. The write value should always be 0. 9 0 R Reserved This bit is always read as 0. The write value should always be 0. 8 0 R Reserved This bit is always read as 0. The write value should always be 0. 7 1 R Reserved This bit is always read as 1. The write value should always be 1. 6 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 4 MSTP5 MSTP4 1 1 All 0 R/W R/W R A/D converter (A/D1) A/D converter (A/D0) Reserved These bits are always read as 0. The write value should always be 0. 11, 10 3 to 0 Rev.2.00 Sep. 27, 2007 Page 394 of 448 REJ09B0394-0200 17. Power-Down Modes 17.3 17.3.1 Operation Sleep Mode Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0, the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers are retained. Peripheral functions except the CPU do not stop. Clearing Sleep Mode: Sleep mode is cleared by the conditions below. * Clearing by the power on reset When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven high after the elapse of the specified reset input period, the CPU starts the reset exception handling. Also, when the internal power on reset is occurred, sleep mode is cleared. * Clearing by the manual reset When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual reset state and thus sleep mode is cleared. Also, when the internal manual reset is occurred, sleep mode is cleared. Notes on Using Sleep Mode * There are 4 conditions to clear sleep mode. (1) Clearing by an interrupt (2) Clearing by DTC address error (3) Clearing by the power-on reset (4) Clearing by the manual reset When clearing sleep mode by (1) or (2), CPU may run out of control. Please clear sleep mode by (3) or (4), don't use (1) or (2). * Do not use DTC module or AUD module during sleep mode. Rev.2.00 Sep. 27, 2007 Page 395 of 448 REJ09B0394-0200 17. Power-Down Modes 17.3.2 Software Standby Mode Transition to Software Standby Mode: A transition is made to software standby mode if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In this mode, the CPU, on-chip peripheral functions, and the oscillator, all stop. However, the contents of the CPU's internal registers and on-chip RAM data (when the RAME bit in SYSCR is 0) are retained as long as the specified voltage is supplied. There are two types of onchip peripheral module registers; ones which are initialized by software standby mode, and those not initialized by that mode. For details, refer to section 18.3, Register States in Each Operating Mode. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port either to "retained" or "high-impedance". For the state of pins, refer to appendix A, Pin States. In software standby mode, the oscillator stops and thus power consumption is significantly reduced. Clearing Software Standby Mode: Software standby mode is cleared by the condition below. * Clearing by the NMI interrupt input When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started. This clock pulse is supplied only to the watchdog timer (WDT). After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and the NMI exception handling is started. When clearing software standby mode by the NMI interrupt, set CKS2 to CKS0 bits so that the WDT overflow period will be longer than the oscillation stabilization time. When software standby mode is cleared by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from standby mode (when the clock is initiated after the oscillation stabilization). When software standby mode is cleared by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). * Clearing by the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset exception handling. Rev.2.00 Sep. 27, 2007 Page 396 of 448 REJ09B0394-0200 17. Power-Down Modes * Clearing by the IRQ interrupt input When the IRQEL bit in the standby control register (SBYCR) is set to 1 and when the falling edge or rising edge of the IRQ pin (selected by the IRQ3S to IRQ0S bits in ICR1 of the interrupt controller (INTC) and the IRQ3ES [1:0] to IRQ0ES [1:0] bits in ICR2) is detected, clock oscillation is started.* This clock pulse is supplied only to the watchdog timer (WDT). The IRQ interrupt priority level should be higher than the interrupt mask level set in the status register (SR) of the CPU before the transition to software standby mode. After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and the IRQ exception handling is started. When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the WDT overflow period will be longer than the oscillation stabilization time. When software standby mode is cleared by the falling edge or both edges of the IRQ pin, the IRQ pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). When software standby mode is cleared by the rising edge of the IRQ pin, the IRQ pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). Note: * When the IRQ pin is set to falling-edge detection or both-edge detection, clock oscillation starts at falling-edge detection. When the IRQ pin is set to rising-edge detection, clock oscillation starts at rising-edge detection. Do not set the IRQ pin to low-level detection. Software Standby Mode Application Example: Figure 17.2 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at a rising edge of the NMI pin. In this example, when the NMI pin is driven low while the NMI edge select bit (NMIE) in ICR1 is 0 (falling edge detection), an NMI interrupt is accepted. Then, the NMIE bit is set to 1 (rising edge detection) in the NMI exception service routine, the SSBY bit in SBYCR is set to 1, and a SLEEP instruction is executed to transfer to software standby mode. Software standby mode is cleared by driving the NMI pin from low to high. Rev.2.00 Sep. 27, 2007 Page 397 of 448 REJ09B0394-0200 17. Power-Down Modes Oscillator CK NMI input NMIE bit SSBY bit LSI state NMI Program exception execution state handling Exception service routine Software standby mode Oscillation WDT start time setting time Oscillation stabilization time NMI exception handling Figure 17.2 NMI Timing in Software Standby Mode 17.3.3 Module Standby Mode Module standby mode can be set for individual on-chip peripheral functions. When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module standby mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the module starts operating at the end of the bus cycle. In module standby mode, the internal states of modules are initialized. After reset clearing, the SCI, MTU, CMT, and A/D converter are in module standby mode. When an on-chip peripheral module is in module standby mode, read/write access to its registers is disabled. Rev.2.00 Sep. 27, 2007 Page 398 of 448 REJ09B0394-0200 17. Power-Down Modes 17.4 17.4.1 Usage Notes I/O Port Status When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 17.4.2 Current Consumption during Oscillation Stabilization Wait Period Current consumption increases during the oscillation stabilization wait period. 17.4.3 On-Chip Peripheral Module Interrupt Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the CPU enters module standby mode while an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode. 17.4.4 Writing to MSTCR1 and MSTCR2 MSTCR1 and MSTCR2 should only be written to by the CPU. Rev.2.00 Sep. 27, 2007 Page 399 of 448 REJ09B0394-0200 17. Power-Down Modes Rev.2.00 Sep. 27, 2007 Page 400 of 448 REJ09B0394-0200 18. List of Registers Section 18 List of Registers The column "Access Size" shows the number of bits. The column "Access States" shows the number of access states, in units of cycles, of the specified reference clock. B, W, and L in the column represent 8-bit, 16-bit, and 32-bit access, respectively. 18.1 Register Addresses (Order of Address) Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFFF8000 to H'FFFF81BF H'FFFF81C0 H'FFFF81C1 H'FFFF81C2 H'FFFF81C3 H'FFFF81C4 H'FFFF81C5 H'FFFF81C6 H'FFFF81C7 to H'FFFF81CF H'FFFF81D0 H'FFFF81D1 H'FFFF81D2 H'FFFF81D3 H'FFFF81D4 H'FFFF81D5 H'FFFF81D6 H'FFFF81D7 to H'FFFF81FF H'FFFF8200 H'FFFF8201 H'FFFF8202 H'FFFF8203 H'FFFF8204 H'FFFF8205 8, 16, 32 MTU (channels 3 8 and 4) 8, 16 8 8, 16, 32 8 In P cycles B: 2 W: 2 L: 4 SCI 8, 16 (channel 3) 8 8, 16 8 8, 16 8 8 Module Access Size Access States In P cycles B: 2 W: 4 Register Name Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit data register_3 Serial status register_3 Receive data register_3 Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 SCI 8, 16 (channel 2) 8 8, 16 8 8, 16 8 8 Serial direction control register_2 SDCR_2 Serial direction control register_3 SDCR_3 Rev.2.00 Sep. 27, 2007 Page 401 of 448 REJ09B0394-0200 18. List of Registers Access Size Access States In P cycles B: 2 W: 2 L: 4 Register Name Timer I/O control register H_4 Timer I/O control register L_4 Abbreviation TIORH_4 TIORL_4 Bits 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 Address H'FFFF8206 H'FFFF8207 H'FFFF8208 H'FFFF8209 H'FFFF820A H'FFFF820B H'FFFF820C H'FFFF820D H'FFFF820E H'FFFF820F H'FFFF8210 H'FFFF8212 H'FFFF8214 H'FFFF8216 H'FFFF8218 H'FFFF821A H'FFFF821C H'FFFF821E H'FFFF8220 H'FFFF8222 H'FFFF8224 H'FFFF8226 H'FFFF8228 H'FFFF822A H'FFFF822C H'FFFF822D H'FFFF822E to H'FFFF823F H'FFFF8240 H'FFFF8241 H'FFFF8242 to H'FFFF825F Module Timer interrupt enable register_3 TIER_3 Timer interrupt enable register_4 TIER_4 Timer output master enable register Timer output control register Timer gate control register Timer counter_3 Timer counter_4 Timer period data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer sub-counter Timer period buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 Timer start register Timer synchro register TOER TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR MTU 8, 16 (channels 3 8 and 4) 8, 16, 32 8 8, 16 8 8 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 MTU (common) 8, 16 8 In P cycles B: 2 W: 2 Rev.2.00 Sep. 27, 2007 Page 402 of 448 REJ09B0394-0200 18. List of Registers Access Size Access States Register Name Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Abbreviation TCR_0 TMDR_0 TIORH_0 TIORL_0 Bits 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 Address H'FFFF8260 H'FFFF8261 H'FFFF8262 H'FFFF8263 H'FFFF8264 H'FFFF8265 H'FFFF8266 H'FFFF8268 H'FFFF826A H'FFFF826C H'FFFF826E H'FFFF8270 to H'FFFF827F H'FFFF8280 H'FFFF8281 H'FFFF8282 H'FFFF8283 H'FFFF8284 H'FFFF8285 H'FFFF8286 H'FFFF8288 H'FFFF828A H'FFFF828C to H'FFFF829F H'FFFF82A0 H'FFFF82A1 H'FFFF82A2 H'FFFF82A3 H'FFFF82A4 H'FFFF82A5 H'FFFF82A6 Module MTU 8, 16, 32 In P cycles (channel 0) B: 2 8 W: 2 8, 16 L: 4 8 8, 16, 32 8 16 16, 32 16 16, 32 16 8, 16 MTU (channel 1) 8 8 8, 16, 32 8 16 16, 32 16 MTU 8, 16 (channel 2) 8 8 8, 16, 32 8 16 Timer interrupt enable register_0 TIER_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 Timer interrupt enable register_1 TIER_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 Timer interrupt enable register_2 TIER_2 Timer status register_2 Timer counter_2 TSR_2 TCNT_2 Rev.2.00 Sep. 27, 2007 Page 403 of 448 REJ09B0394-0200 18. List of Registers Access Size Access States In P cycles B: 2 W: 2 L: 4 In cycles B: 2 W: 2 L: 4 Register Name Timer general register A_2 Timer general register B_2 Interrupt priority register A Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt control register 1 IRQ status register Interrupt priority register I Interrupt control register 2 Port A data register L Port A I/O register L Port A control register L3 Port A control register L1 Port A control register L2 Port B data register Abbreviation TGRA_2 TGRB_2 IPRA IPRD IPRE IPRF IPRG IPRH ICR1 ISR IPRI ICR2 PADRL PAIORL PACRL3 PACRL1 PACRL2 PBDR Bits 16 16 16 16 16 16 16 16 16 16 16 8 16 16 16 16 16 16 Address H'FFFF82A8 H'FFFF82AA H'FFFF82AC to H'FFFF833F H'FFFF8340 to H'FFFF8347 H'FFFF8348 H'FFFF834A to H'FFFF834D H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A H'FFFF835C H'FFFF835E to H'FFFF8365 H'FFFF8366 H'FFFF8368 to H'FFFF837F H'FFFF8380 to H'FFFF8381 H'FFFF8382 H'FFFF8384 to H'FFFF8385 H'FFFF8386 H'FFFF8388 to H'FFFF8389 H'FFFF838A H'FFFF838C H'FFFF838E H'FFFF8390 H'FFFF8392 to H'FFFF8393 Module MTU 16, 32 (channel 2) 16 INTC 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 I/O PFC PFC 8, 16 8, 16 8, 16 8, 16, 32 8, 16 I/O 8, 16 In cycles B: 2 W: 2 L: 4 Rev.2.00 Sep. 27, 2007 Page 404 of 448 REJ09B0394-0200 18. List of Registers Access Size Access States Register Name Port B I/O register Port B control register 1 Port B control register 2 Port E data register L Port F data register Port E I/O register L Port E I/O register H Port E control register L1 Port E control register L2 Port E control register H Port E data register H Input control/status register 1 Output control/status register Abbreviation PBIOR PBCR1 PBCR2 PEDRL PFDR PEIORL PEIORH PECRL1 PECRL2 PECRH PEDRH ICSR1 OCSR Bits 16 16 16 16 16 16 16 16 16 16 16 16 16 Address H'FFFF8394 H'FFFF8396 to H'FFFF8397 H'FFFF8398 H'FFFF839A Module PFC PFC 8, 16, 32 In cycles B: 2 W: 2 L: 4 8, 16, 32 8, 16 8, 16, 32 8, 16 H'FFFF839C to H'FFFF83AE H'FFFF83B0 H'FFFF83B2 H'FFFF83B4 H'FFFF83B6 H'FFFF83B8 H'FFFF83BA H'FFFF83BC H'FFFF83BE H'FFFF83C0 H'FFFF83C2 I/O MTU PFC I/O 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 In cycles B: 2 8, 16 W: 2 L: 4 8 In P cycles B: 2 W: 2 L: 4 Port G data register PGDR 8 H'FFFF83C4 to H'FFFF83CC H'FFFF83CD I/O Compare match timer start register Compare match timer control/status register_0 Compare match timer counter_0 Compare match timer constant register_0 CMSTR CMCSR_0 CMCNT_0 CMCOR_0 16 16 16 16 H'FFFF83CE to H'FFFF83CF H'FFFF83D0 H'FFFF83D2 H'FFFF83D4 H'FFFF83D6 CMT 8, 16, 32 In cycles B: 2 W: 2 8, 16 L: 4 8, 16, 32 8, 16 Rev.2.00 Sep. 27, 2007 Page 405 of 448 REJ09B0394-0200 18. List of Registers Access Size Access States Register Name Compare match timer control/status register_1 Compare match timer counter_1 Compare match timer constant register_1 A/D data register 8 Abbreviation CMCSR_1 CMCNT_1 CMCOR_1 ADDR8 Bits 16 16 16 16 Address H'FFFF83D8 H'FFFF83DA H'FFFF83DC H'FFFF83DE Module CMT 8, 16, 32 In cycles B: 2 W: 2 8, 16 L: 4 8, 16 H'FFFF83E0 to H'FFFF842E H'FFFF8430 In P cycles B: 3 W: 6 A/D 8, 16 (channel 0) 8, 16 8, 16 8, 16 8, 16 A/D (channel 1) 8, 16 8, 16 8, 16 A/D 8, 16 8 8, 16 8 WDT *1: Write cycle *2: Read cycle 8*2/16*1 16 8 16 8 Power8 down state A/D data register 9 A/D data register 10 A/D data register 11 A/D data register 12 A/D data register 13 A/D data register 14 A/D data register 15 A/D control/status register_0 A/D control/status register_1 A/D control register_0 A/D control register_1 Timer control/status register Timer counter Timer counter Reset control/status register Reset control/status register Standby control register ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADCSR_0 ADCSR_1 ADCR_0 ADCR_1 TCSR TCNT* 1 16 16 16 16 16 16 16 8 8 8 8 8 8 8 1 H'FFFF8432 H'FFFF8434 H'FFFF8436 H'FFFF8438 H'FFFF843A H'FFFF843C H'FFFF843E H'FFFF8440 to H'FFFF847F H'FFFF8480 H'FFFF8481 H'FFFF8482 to H'FFFF8487 H'FFFF8488 H'FFFF8489 H'FFFF848A to H'FFFF860F H'FFFF8610 H'FFFF8610 H'FFFF8611 H'FFFF8612 H'FFFF8613 H'FFFF8614 In cycles B: 3 W: 3 TCNT*2 RSTCSR* 8 8 8 RSTCSR*2 SBYCR In cycles B: 3 Rev.2.00 Sep. 27, 2007 Page 406 of 448 REJ09B0394-0200 18. List of Registers Access Size Access States In P cycles B: 3 W: 3 L: 6 Register Name System control register Abbreviation SYSCR Bits 8 16 16 16 Address H'FFFF8615 to H'FFFF8617 H'FFFF8618 H'FFFF8619 to H'FFFF861B H'FFFF861C H'FFFF861E H'FFFF8620 H'FFFF8622 to H'FFFF8626 H'FFFF8628 to H'FFFF87F3 H'FFFF87F4 H'FFFF87F5 to H'FFFF89FF H'FFFF8A00 to H'FFFFB4F3 Module Power8 down state 8, 16, 32 8, 16 BSC Module standby control register 1 MSTCR1 Module standby control register 2 MSTCR2 Bus control register 1 BCR1 8, 16, 32 In cycles B: 3 W: 3 L: 6 AD trigger select register ADTSR 8 A/D 8 In P cycles B: 3 Rev.2.00 Sep. 27, 2007 Page 407 of 448 REJ09B0394-0200 18. List of Registers 18.2 Register Bits On-chip peripheral module register addresses and bit names are shown in the following table. 16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively. Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SDCR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SDCR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 CCLR2 CCLR2 IOB3 IOD3 IOB3 IOD3 TTGE TTGE CCLR1 CCLR1 IOB2 IOD2 IOB2 IOD2 PSYE BDC CCLR0 CCLR0 BFB BFB IOB1 IOD1 IOB1 IOD1 OE4D N CKEG1 CKEG1 BFA BFA IOB0 IOD0 IOB0 IOD0 TCIEV TCIEV OE4C P DIR CKEG0 CKEG0 MD3 MD3 IOA3 IOC3 IOA3 IOC3 TGIED TGIED OE3D FB TPSC2 TPSC2 MD2 MD2 IOA2 IOC2 IOA2 IOC2 TGIEC TGIEC OE4B WF TPSC1 TPSC1 MD1 MD1 IOA1 IOC1 IOA1 IOC1 TGIEB TGIEB OE4A OLSN VF TPSC0 TPSC0 MD0 MD0 IOA0 IOC0 IOA0 IOC0 TGIEA TGIEA OE3B OLSP UF MTU (channels 3 and 4) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A CHR PE O/E DIR STOP MP CKS1 CKS0 SCI (channel 3) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI (channel 2) Rev.2.00 Sep. 27, 2007 Page 408 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation TCNT_4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MTU (channels 3 and 4) TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCFD TCFD CST4 SYNC4 CCLR2 IOB3 IOD3 TTGE CST3 SYNC3 CCLR1 IOB2 IOD2 CCLR0 BFB IOB1 IOD1 TCFV TCFV CKEG1 BFA IOB0 IOD0 TCIEV TCFV TGFD TGFD CKEG0 MD3 IOA3 IOC3 TGIED TGFD TGFC TGFC CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TGFB TGFB CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TGFA TGFA CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA MTU (channel 0) Rev.2.00 Sep. 27, 2007 Page 409 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MTU (channel 0) TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 MD3 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA MTU (channel 1) TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 MD3 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA MTU (channel 2) TGRA_2 TGRB_2 Rev.2.00 Sep. 27, 2007 Page 410 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation IPRA Bit 7 IRQ0 IRQ2 Bit 6 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 A/D0,1 CMT0 WDT IRQ1S IRQ1F SCI2 IRQ0ES0 PA14DR PA6DR PA14IOR PA6IOR Bit 5 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 A/D0,1 CMT0 WDT IRQ2S IRQ2F SCI2 IRQ1ES1 PA13DR PA5DR PA13IOR PA5IOR Bit 4 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 A/D0,1 CMT0 WDT IRQ3S IRQ3F SCI2 IRQ1ES0 PA12DR PA4DR PA12IOR PA4IOR Bit 3 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 CMT1 I/O(MTU) SCI3 IRQ2ES1 PA11DR PA3DR PA11IOR PA3IOR Bit 2 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 CMT1 I/O(MTU) SCI3 IRQ2ES0 PA10DR PA2DR PA10IOR PA2IOR Bit 1 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 CMT1 I/O(MTU) SCI3 IRQ3ES1 PA9DR PA1DR PA9IOR PA1IOR Bit 0 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 CMT1 I/O(MTU) NMIE SCI3 IRQ3ES0 PA8DR PA0DR PA8IOR PA0IOR PA8MD2 PA0MD2 Module INTC IPRD MTU0 MTU1 IPRE MTU2 MTU3 IPRF MTU4 IPRG A/D0,1 CMT0 IPRH WDT ICR1 NMIL IRQ0S ISR IRQ0F IPRI SCI2 ICR2 IRQ0ES1 PADRL PA15DR PA7DR Port A PAIORL PA15IOR PA7IOR PACRL3 PA15MD2 PA14MD2 PA13MD2 PA12MD2 PA11MD2 PA10MD2 PA9MD2 PA7MD2 PA6MD2 PA5MD2 PA4MD2 PA3MD2 PA2MD2 PA1MD2 PACRL1 PA15MD1 PA15MD0 PA14MD1 PA14MD0 PA13MD1 PA13MD0 PA12MD1 PA12MD0 PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA9MD1 PA9MD0 PA5MD0 PA1MD0 PA8MD1 PA4MD1 PA0MD1 PA8MD0 PA4MD0 PA0MD0 PACRL2 PA7MD1 PA3MD1 PA7MD0 PA3MD0 PA6MD1 PA2MD1 PA6MD0 PA2MD0 PA5MD1 PA1MD1 Rev.2.00 Sep. 27, 2007 Page 411 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation PBDR Bit 7 Bit 6 PB3MD0 PE14DR PE6DR PF14DR PF6DR Bit 5 PB5DR PB5IOR PB5MD2 PB2MD1 PE13DR PE5DR PF13DR PF5DR Bit 4 PB4DR PB4 IOR PB4MD2 PB2MD0 PE12DR PE4DR PF12DR PF4DR Bit 3 PB3DR PB3 IOR PB3MD2 PB5MD1 PE11DR PE3DR PF11DR PF3DR Bit 2 PB2DR PB2 IOR PB2MD2 PB5MD0 PE10DR PE2DR PF10DR PF2DR Bit 1 PB4MD1 PE9DR PE1DR PF9DR PF1DR Bit 0 PB4MD0 PE8DR PE0DR PF8DR PF0DR PE8 IOR PE0IOR PE16IOR Module Port B PBIOR PBCR1 PBCR2 PB3MD1 PEDRL PE15DR PE7DR Port E PFDR PF15DR PF7DR Port F PEIORL PE15IOR PE7IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE6IOR PE5IOR PE21IOR PE4IOR PE20IOR PE3IOR PE19IOR PE2IOR PE18IOR PE1IOR PE17IOR Port E PEIORH PECRL1 PE15MD1 PE15MD0 PE14MD1 PE14MD0 PE13MD1 PE13MD0 PE12MD1 PE12MD0 PE11MD1 PE11MD0 PE10MD1 PE10MD0 PE9MD1 PE9MD0 PE5MD0 PE1MD0 PE8MD1 PE4MD1 PE0MD1 PE8MD0 PE4MD0 PE0MD0 PECRL2 PE7MD1 PE3MD1 PE7MD0 PE3MD0 PE6MD1 PE2MD1 PE6MD0 PE2MD0 PE5MD1 PE1MD1 PECRH PE21MD1 PE21MD0 PE20MD1 PE20MD0 PE19MD1 PE19MD0 PE18MD1 PE18MD0 PE17MD1 PE17MD0 PE16MD1 PE16MD0 PEDRH ICSR1 POE3F POE3M1 OCSR OSF PGDR POE2F POE3M0 PE21DR POE1F POE2M1 PE20DR POE0F POE2M0 PE19DR POE1M1 PG3DR PE18DR POE1M0 PG2DR PE17DR POE0M1 OCE PG1DR PE16DR PIE POE0M0 OIE PG0DR Port G MTU Rev.2.00 Sep. 27, 2007 Page 412 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation CMSTR Bit 7 Bit 6 CMIE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STR1 CKS1 Bit 0 STR0 CKS0 Module CMT CMCSR_0 CMF CMCNT_0 CMCOR_0 CMCSR_1 CMF CMIE CKS1 CKS0 CMCNT_1 CMCOR_1 ADDR8 AD9 AD1 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE ADIE CKS1 CKS1 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD7 ADM1 ADM1 CKS0 CKS0 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD6 ADM0 ADM0 ADST ADST AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD5 ADCS ADCS AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD4 CH2 CH2 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 CH1 CH1 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 CH0 CH0 A/D ADDR9 AD9 AD1 ADDR10 AD9 AD1 ADDR11 AD9 AD1 ADDR12 AD9 AD1 ADDR13 AD9 AD1 ADDR14 AD9 AD1 ADDR15 AD9 AD1 ADCSR_0 ADCSR_1 ADCR_0 ADCR_1 ADF ADF TRGE TRGE Rev.2.00 Sep. 27, 2007 Page 413 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation TCSR TCNT RSTCSR SBYCR SYSCR MSTCR1 WOVF SSBY MSTCR2 BCR1 ADTSR RSTE HIZ RSTS MSTP13 MSTP5 MSTP12 MSTP4 MSTP27 MSTP19 TRG1S1 MSTP26 MSTP18 TRG1S0 TRG0S1 IRQEL RAME TRG0S0 A/D BSC Power-down state Bit 7 OVF Bit 6 WT/IT Bit 5 TME Bit 4 Bit 3 Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Module WDT MTURWE Rev.2.00 Sep. 27, 2007 Page 414 of 448 REJ09B0394-0200 18. List of Registers 18.3 Register States in Each Operating Mode Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Manual Reset Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held MTU (channels 3 and 4) SCI (channel 3) Module SCI (channel 2) Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SDCR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SDCR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR Rev.2.00 Sep. 27, 2007 Page 415 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Manual Reset Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MTU (channels 3 and 4) MTU (channel 0) Rev.2.00 Sep. 27, 2007 Page 416 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 IPRA IPRD IPRE IPRF IPRG IPRH ICR1 ISR IPRI ICR2 PADRL PAIORL PACRL3 PACRL1 PACRL2 PBDR PBIOR PBCR1 PBCR2 PEDRL PFDR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Software Manual Reset Standby Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MTU (channel 2) INTC Port A Port B Port E Port F Rev.2.00 Sep. 27, 2007 Page 417 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation PEIORL PEIORH PECRL1 PECRL2 PECRH PEDRH ICSR1 OCSR PGDR CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADCSR_0 ADCSR_1 ADCR_0 ADCR_1 TCSR TCNT RSTCSR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Manual Reset Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Initialized Module Standby Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Port E MTU Port G CMT A/D WDT Rev.2.00 Sep. 27, 2007 Page 418 of 448 REJ09B0394-0200 18. List of Registers Register Abbreviation SBYCR SYSCR MSTCR1 MSTCR2 BCR1 ADTSR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Software Manual Reset Standby Initialized Held Held Held Held Held Held Held Held Held Held Held Module Standby Sleep Held Held Held Held Held Held Module Power-down state BSC A/D Rev.2.00 Sep. 27, 2007 Page 419 of 448 REJ09B0394-0200 18. List of Registers Rev.2.00 Sep. 27, 2007 Page 420 of 448 REJ09B0394-0200 19. Electrical Characteristics Section 19 Electrical Characteristics 19.1 Absolute Maximum Ratings Table 19.1 shows the absolute maximum ratings. Table 19.1 Absolute Maximum Ratings Item Power supply voltage Input voltage EXTAL pin All pins other than analog input and EXTAL pins Analog supply voltage Analog input voltage Operating temperature Standard product* Wide temperature-range product* Storage temperature Tstg Symbol VCC Vin Vin AVCC VAN Topr Rating -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 -20 to +75 -40 to +85 -55 to +125 C Unit V V V V V C [Operating precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev.2.00 Sep. 27, 2007 Page 421 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.2 DC Characteristics Table 19.2 DC Characteristics Conditions: VCC = 4.0 to 5.5 V, AVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)* Item Input high-level voltage (except Schmitt trigger input voltage) RES, MRES, NMI, FWP, MD3 to MD0 EXTAL A/D port Other input pins Input low-level voltage (except Schmitt trigger input voltage) Schmitt trigger input voltage RES, MRES, NMI, FWP, MD3 to MD0, EXTAL Other input pins IRQ3 to IRQ0, VT+ POE3 to POE0, TCLKA VT- to TCLKD, TIOC0A to VT+-VT- TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D RES, MRES, NMI, FWP, MD3 to MD0 Ports F and G Other input pins Three-state leak Port A, B, E current (while OFF) Output highlevel voltage Output lowlevel voltage Pull-up resistor All output pins | Itsi | | Iin | VIL Symbol Min VIH VCC -0.7 VCC -0.7 2.2 2.2 -0.3 Typ Max VCC +0.3 VCC +0.3 AVCC +0.3 VCC +0.3 0.5 Unit V V V V V Measurement Conditions -0.3 VCC -0.5 -0.3 0.4 0.8 VCC +0.3 1.0 V V V V Input leak current 1.0 1.0 1.0 1.0 A A A A Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V Vin = 0.5 to VCC -0.5 V Vin = 0.5 to VCC -0.5 V IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 15 mA VOH VCC -0.5 VCC -0.5 50 0.4 1.5 80 V V V V k All output pins PE9, PE11 to PE15 PA15 to PA12, PE21 to PE16 VOL Rpull 20 Rev.2.00 Sep. 27, 2007 Page 422 of 448 REJ09B0394-0200 19. Electrical Characteristics Measurement Conditions Vin = 0 V = 1 MHz Ta = 25C = 40 MHz = 40 MHz = 40 MHz = 40 MHz Ta 50C 50C < Ta Item Input capacitance RES NMI All other input pins Current consumption Normal Clock 1:1 operation Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Standby Symbol Min Cin ICC VRAM 2.0 Typ 110 100 70 60 1 3 Max 80 50 20 130 120 90 80 10 50 5 5 Unit pF pF pF mA mA mA mA A A mA A V Analog supply current During A/D conversion, AICC A/D converter idle state During standby RAM standby voltage VCC [Operating precautions] 1. When the A/D converter is not used, the AVCC, and AVSS pins should not be open. 2. The current consumption is measured when VIHmin = VCC -0.5 V, VIL = 0.5 V, with all output pins unloaded. Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev.2.00 Sep. 27, 2007 Page 423 of 448 REJ09B0394-0200 19. Electrical Characteristics Table 19.3 Permitted Output Current Values Conditions: VCC = 4.0 V to 0.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 1 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 1 product)* Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL -IOH -IOH Min Typ Max 2.0* 110 2.0 25 2 Unit mA mA mA mA [Operating precautions] To assure LSI reliability, do not exceed the output values listed in this table. Note: 1. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. IOL= 15 mA (max) about the pins PE9, PE11 to PE15. However, three pins at most are permitted to have simultaneously IOL > 2.0 mA among these pins. Rev.2.00 Sep. 27, 2007 Page 424 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.3 19.3.1 AC Characteristics Test Conditions for the AC Characteristics high level: VIH minimum value, low level: VIL maximum value high level: 2.0 V, low level: 0.8 V IOL Input reference levels Output reference levels LSI output pin DUT output CL 30 pF V VREF IOH CL is a total value that includes the capacitance of measurement equipment, and is set as follows: 30 pF: IRQOUT 30 pF: Port output pins and peripheral module output pins other than the above It is assumed that IOL = 1.6 mA, IOH = 200 A in the test conditions. Figure 19.1 Output Load Circuit Rev.2.00 Sep. 27, 2007 Page 425 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.3.2 Clock Timing Table 19.4 shows the clock timing. Table 19.4 Clock Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)* Item Operating frequency Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby return oscillation settling time Note: * Symbol Min fop tcyc tCL tCH tCR tCF fEX tEXcyc tEXL tEXH tEXR tEXF tOSC1 tOSC2 10 25 4 4 4 100 45 45 10 10 25 Max 40 250 5 5 10.0 250 5 5 100 Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms ns Figure 19.4 Figure 19.3 Figures Figure 19.2 Clock cycle time for on-chip peripheral modules tpcyc See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev.2.00 Sep. 27, 2007 Page 426 of 448 REJ09B0394-0200 19. Electrical Characteristics tcyc tCH tCL VOH CK 1/2VCC VOH VOL tCF VOL VOH 1/2VCC tCR Figure 19.2 System Clock Timing tEXcyc tEXH tEXL EXTAL VIH 1/2VCC VIH VIL tEXF VIL VIH 1/2VCC tEXR Figure 19.3 EXTAL Clock Input Timing CK VCC RES VCC min tOSC1 Figure 19.4 Oscillation Settling Time Rev.2.00 Sep. 27, 2007 Page 427 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.3.3 Control Signal Timing Table 19.5 shows control signal timing. Table 19.5 Control Signal Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 1 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 1 product)* Item RES rise time, fall time RES pulse width RES setup time MRES pulse width MRES setup time MD3 to MD0, FWP setup time NMI rise time, fall time NMI setup time IRQ3 to IRQ0 setup time* (edge detection) 2 2 Symbol tRESr, tRESf tRESW tRESS tMRESW tMRESS tMDS tNMIr, tNMIIf tNMIS tIRQES tIRQLS tNMIH tIRQEH tIRQOD Min 25 19 20 19 20 19 19 19 19 19 Max 200 200 100 Unit ns tcyc ns tcyc ns tcyc ns ns ns ns ns ns ns Figures Figure 19.5 Figure 19.6 Figure 19.7 IRQ3 to IRQ0 setup time* (level detection) NMI hold time IRQ3 to IRQ0 hold time IRQOUT output delay time Figure 19.8 [Operating precautions] Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. The RES, MRES, NMI and IRQ3 to IRQ0 signals are asynchronous inputs, but when the setup times shown here are observed, the signals are considered to have been changed at clock rise (RES, MRES) or fall (NMI and IRQ3 to IRQ0). If the setup times are not observed, detection of these signals may be delayed until the next clock rise or fall. Rev.2.00 Sep. 27, 2007 Page 428 of 448 REJ09B0394-0200 19. Electrical Characteristics CK tRESS tRESW VIL tMDS tRESS VOH VIH RES VIH VIL MD3 to MD0 FWP VIH VIL Figure 19.5 Reset Input Timing CK tMRESS MRES tMRESS VIH VIL tMRESW VIL Figure 19.6 Reset Input Timing Rev.2.00 Sep. 27, 2007 Page 429 of 448 REJ09B0394-0200 19. Electrical Characteristics CK VOL VOL tNMIH NMI VIH VIL tIRQEH IRQ edge tNMIS VIH VIL tIRQES VIH VIL tIRQLS IRQ level VIL Figure 19.7 Interrupt Signal Input Timing VOH tIRQOD tIRQOD CK VOH IRQOUT VOL Figure 19.8 Interrupt Signal Output Timing Rev.2.00 Sep. 27, 2007 Page 430 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.3.4 Multi-Function Timer Pulse Unit (MPU) Timing Table 19.6 shows Multi-Function timer pulse unit timing. Table 19.6 Multi-Function Timer Pulse Unit Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product*), Ta = -40C to +85C (Wide temperature-range product*) Item Output compare output delay time Input capture input setup time Timer input setup time Timer clock pulse width (single edge specified) Timer clock pulse width (both edges specified) Timer clock pulse width (phase count mode) Note: * Symbol tTOCD tTICS tTCKS tTCKWH/L tTCKWH/L tTCKWH/L Min 19 20 1.5 2.5 2.5 Max 100 Unit ns ns ns tpcyc tpcyc tpcyc Figure 19.10 Figures Figure 19.9 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK tTOCD Output compare output tTICS Input capture input Figure 19.9 MTU Input/Output Timing Rev.2.00 Sep. 27, 2007 Page 431 of 448 REJ09B0394-0200 19. Electrical Characteristics CK tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 19.10 MTU Clock Input Timing 19.3.5 I/O Port Timing Table 19.7 shows I/O port timing. Table 19.7 I/O Port Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product*), Ta = -40C to +85C (Wide temperature-range product*) Item Port output data delay time Port input hold time Port input setup time Symbol tPWD tPRH tPRS Min 19 19 Max 100 Unit ns ns ns Figures Figure 19.11 [Operating precautions] The port input signals are asynchronous. They are, however, considered to have been changed at CK clock fall with two-state intervals shown in figure 19.11. If the setup times shown here are not observed, detection may be delayed until the clock fall two states after that timing. Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev.2.00 Sep. 27, 2007 Page 432 of 448 REJ09B0394-0200 19. Electrical Characteristics CK tPRS Port (read) tPWD Port (write) tPRH Figure 19.11 I/O Port Input/Output Timing 19.3.6 Watchdog Timer (WDT) Timing Table 19.8 shows watchdog timer timing. Table 19.8 Watchdog Timer Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)* Item WDTOVF delay time Note: * Symbol tWOVD Min Max 100 Unit ns Figures Figure 19.12 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK VOH tWOVD VOH tWOVD WDTOVF Figure 19.12 WDT Timing Rev.2.00 Sep. 27, 2007 Page 433 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.3.7 Serial Communication Interface (SCI) Timing Table 19.9 shows serial communication interface timing. Table 19.9 Serial Communication Interface Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)* Item Input clock cycle Input clock cycle (clock sync) Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Received data setup time Received data hold time Symbol tscyc tscyc tsckw tsckr tsckf tTxD tRxS tRxH Min 4 6 0.4 100 100 Max 0.6 1.5 1.5 100 Unit tpcyc tpcyc tscyc tpcyc tpcyc ns ns ns Figure 19.14 Figures Figure 19.13 [Operating precautions] The inputs and outputs are asynchronous in asynchronous mode, but as shown in figure 19.14, the received data is considered to have been changed at CK clock rise (two-clock intervals). The transmit signals change with a reference of CK clock rise (two-clock intervals). Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. tsckw VIH SCK2, SCK3 VIH VIL VIL tsckr VIH VIH tsckf VIL tscyc Figure 19.13 Input Clock Timing Rev.2.00 Sep. 27, 2007 Page 434 of 448 REJ09B0394-0200 19. Electrical Characteristics SCI input/output timing (clock synchronous mode) tscyc SCK2, SCK3 (input/output) tTxD TxD2, TxD3 (transmit data) tRxS RxD2, RxD3 (receive data) tRxH SCI input/output timing (asynchronous mode) T1 VOH CK tTxD TxD2, TxD3 (transmit data) tRxS RxD2, RxD3 (receive data) tRxH VOH Tn Figure 19.14 SCI Input/Output Timing Rev.2.00 Sep. 27, 2007 Page 435 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.3.8 Output Enable (POE) Timing Table 19.10 Output Enable Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product*), Ta = -40C to +85C (Wide temperature-range product*) Item POE input setup time POE input pulse width Note: * Symbol tPOES tPOEW Min 100 1.5 Max Unit ns tcyc Figures Figure 19.15 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK tPOES POE input tPOEW Figure 19.15 POE Input/Output Timing 19.3.9 A/D Converter Timing Table 19.11 shows A/D converter timing. Table 19.11 A/D Converter Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product*), Ta = -40C to +85C (Wide temperature-range product*) Item External trigger input start delay time Note: * Symbol tTRGS Min 50 Typ Max Unit ns Figure Figure 19.16 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev.2.00 Sep. 27, 2007 Page 436 of 448 REJ09B0394-0200 19. Electrical Characteristics 3 to 5 states VOH CK ADTRG input tTRGS ADCR (ADST = 1 set) Figure 19.16 External Trigger Input Timing Rev.2.00 Sep. 27, 2007 Page 437 of 448 REJ09B0394-0200 19. Electrical Characteristics 19.4 A/D Converter Characteristics Table 19.12 shows A/D converter characteristics. Table 19.12 A/D Converter Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 1 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range product)* Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Non-linear error Offset error Full-scale error Quantization error Absolute error Min 10 Typ 10 Max 10/5.4 6.7* /5.4* 20 3/1* 3 2 2 2 3 3 3 2 3 Unit bit s pF k LSB LSB LSB LSB 2 3 3.0* /5.0* 3.0* /5.0* 3.0* /5.0* 0.5 4.0* /6.0* LSB Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. Value when (CKS1, 0) = (1, 1) and tpcyc = 50 ns 3. Value when (CKS1, 0) = (1, 1) and tpcyc = 40 ns Rev.2.00 Sep. 27, 2007 Page 438 of 448 REJ09B0394-0200 Appendix A Pin States Appendix A Pin States The initial values differ in each MCU operating mode. For details, refer to section 13, Pin Function Controller (PFC). Table A.1 Pin States Pin State Reset State Type Clock Pin Name XTAL EXTAL PLLCAP System Control RES MRES WDTOVF Operation Mode Control MD0 to MD3 FWP Interrupt NMI IRQ0 to IRQ3 IRQOUT MTU TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3C TIOC3B, TIOC3D TIOC4A to TIOC4D Port control SCI POE0 to POE3 SCK2, SCK3 RXD2, RXD3 TXD2, TXD3 Z Z Z Z I I/O I O Z Z Z O* 1 2 Pin Function Power-Down State Software Standby L I I I Z* O I I I Z* 4 1 2 Power-On Manual O I I I Z O* I I I Z Z Z Z 3 Sleep O I I I I O I I I I O I O I I I I O I I I I O I I/O K* Z K* 1 I/O Z I/O Z* I/O I I/O I O Rev.2.00 Sep. 27, 2007 Page 439 of 448 REJ09B0394-0200 Appendix A Pin States Pin Function Reset State Type A/D converter Pin Name AN8 to AN15 ADTRG I/O port PA0 to PA15 PB2 to PB5 PE0 to PE8, PE10, PE16 to PE21 PE9, PE11 to PE15 PF8 to PF15 PG0 to PG3 Z Z Z I/O I I Z* Z Z 2 Pin State Power-Down State Software Standby Z Z K* 1 Power-On Manual Z Z Z I I I/O Sleep I I I/O I/O I I Legend: I: Input O: Output H: High-level output L: Low-level output Z: High impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. When the HIZ bit in SBYCR is set to 1, the output pins enter their high-impedance state. 2. Those pins multiplexed with large-current pins (PE9, PE11 to PE15) unconditionally enter their high-impedance state. 3. This pin operates as an input pin during a power-on reset. This pin should be pulled up to avoid malfunction. 4. This pin operates as an input pin when the IRQEL bit in SBYCR is cleared to 0. Rev.2.00 Sep. 27, 2007 Page 440 of 448 REJ09B0394-0200 Appendix B Product Lineup Appendix B Product Lineup Product Type SH7101 Mask ROM version Standard product Part No. HD6437101 Package (Package Code) QFP-80 (FP-80Q) Rev.2.00 Sep. 27, 2007 Page 441 of 448 REJ09B0394-0200 Appendix B Product Lineup Rev.2.00 Sep. 27, 2007 Page 442 of 448 REJ09B0394-0200 Appendix C Package Dimensions Appendix C Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-QFP80-14x14-0.65 RENESAS Code PRQP0080JD-A Previous Code FP-80Q/FP-80QV MASS[Typ.] 1.2g HD *1 D 60 41 61 40 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section 80 21 Reference Dimension in Millimeters Symbol 1 ZD 20 c F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 17.0 17.2 17.4 17.0 17.2 17.4 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0 8 0.65 0.12 0.10 0.83 0.83 0.6 0.8 1.0 1.6 Min ZE Figure C.1 FP-80Q Rev.2.00 Sep. 27, 2007 Page 443 of 448 REJ09B0394-0200 A A2 Appendix C Package Dimensions Rev.2.00 Sep. 27, 2007 Page 444 of 448 REJ09B0394-0200 Index Index A/D conversion time............................... 335 A/D converter ......................................... 325 Absolute maximum ratings..................... 421 Address error exception processing .......... 60 Address map ............................................. 45 Addressing modes..................................... 20 Buffer operation...................................... 145 Bus state controller ................................... 87 Byte........................................................... 15 Cascaded operation ................................. 149 Clock mode............................................... 43 Clock pulse generator ............................... 47 Clocked synchronous communication .... 313 Compare match....................................... 139 Compare match timer.............................. 343 Continuous scan mode ............................ 333 Control registers........................................ 13 Crystal Resonator...................................... 47 Data Formats............................................. 15 Delayed branch instructions...................... 17 Exception processing ................................ 53 Exception processing state........................ 42 Exception processing vector table ............ 55 External clock ........................................... 49 Free-running counters ............................. 138 General illegal instruction exception processing ................................................. 63 General registers ....................................... 13 Global Base Register (GBR)..................... 14 High-impedance state ............................. 252 I/O Ports ..................................................371 Illegal slot exception processing ...............63 Input capture ...........................................141 Interrupt controller ....................................67 Interrupt exception processing ..................61 Interrupt response time..............................84 Interval Timer Mode ...............................271 IRQ interrupts ...........................................75 Longword..................................................15 Manual reset..............................................58 Mask ROM..............................................383 Module standby mode.............................398 Multi-function timer pulse unit .................91 Multiply-and-Accumulate Registers (MAC) ..................................................................14 Multiprocessor communication function.307 NMI interrupt ............................................75 On-chip peripheral module interrupts .......77 Operating modes .......................................43 Overrun error...........................................303 Periodic counter ......................................137 Phase counting mode ..............................156 Pin function controller ............................353 Pin functions in each operating mode .....353 Power-down modes.................................387 Power-down state......................................42 Power-on reset...........................................57 Procedure Register (PR)............................14 Processing states .......................................41 Program Counter (PC) ..............................14 Program execution state ............................42 PWM mode .............................................150 Rev.2.00 Sep. 27, 2007 Page 445 of 448 REJ09B0394-0200 Index RAM ....................................................... 385 Reading from TCNT, TCSR, and RSTCSR ................................................................ 274 Registers ADCR ......................... 330, 406, 413, 418 ADCSR....................... 329, 406, 413, 418 ADDR................................................. 328 ADTSR ....................... 332, 407, 414, 419 BCR1 ............................ 89, 407, 414, 419 BRR ............................ 287, 401, 408, 415 CMCNT ...................... 346, 405, 413, 418 CMCOR...................... 346, 405, 413, 418 CMCSR ...................... 345, 405, 413, 418 CMSTR....................... 344, 405, 413, 418 ICR1 ............................. 69, 404, 411, 417 ICR2 ............................. 70, 404, 411, 417 ICSR1 ......................... 254, 405, 412, 418 IPR ................................ 73, 404, 411, 417 ISR ................................ 72, 404, 411, 417 MSTCR....................... 393, 407, 414, 419 OCSR.......................... 257, 405, 412, 418 PACRL ....................... 361, 404, 411, 417 PADRL ....................... 372, 404, 411, 417 PAIORL...................... 360, 404, 411, 417 PBCR .......................... 365, 405, 412, 417 PBDR.......................... 374, 404, 412, 417 PBIOR ........................ 364, 405, 412, 417 PECRH ....................... 366, 405, 412, 418 PECRL........................ 366, 405, 412, 418 PEDRH ....................... 377, 405, 412, 418 PEDRL........................ 377, 405, 412, 417 PEIORH...................... 366, 405, 412, 418 PEIORL ...................... 366, 405, 412, 418 PFDR .......................... 379, 405, 412, 417 PGDR.......................... 381, 405, 412, 418 RDR ............................ 280, 401, 408, 415 RSR..................................................... 280 RSTCSR ............................. 268, 406, 418 SBYCR ....................... 390, 406, 414, 419 SCR............................. 283, 401, 408, 415 Rev.2.00 Sep. 27, 2007 Page 446 of 448 REJ09B0394-0200 SDCR .......................... 287, 401, 408, 415 SMR ............................ 281, 401, 408, 415 SSR ............................. 285, 401, 408, 415 SYSCR........................ 392, 407, 414, 419 TCBR .......................... 135, 402, 409, 416 TCDR.......................... 135, 402, 409, 415 TCNT ......................... 126, 265, 402, 406, ................................ 408, 414, 415, 418 TCNTS........................ 135, 402, 409, 416 TCR............................... 98, 401, 408, 415 TCSR .......................... 266, 406, 414, 418 TDDR.......................... 135, 402, 409, 415 TDR ............................ 280, 401, 408, 415 TGCR.......................... 133, 402, 408, 415 TGR ............................ 127, 402, 409, 416 TIER............................ 122, 402, 408, 415 TIOR ........................... 104, 401, 408, 415 TMDR ......................... 102, 401, 408, 415 TOCR.......................... 131, 402, 408, 415 TOER .......................... 130, 402, 408, 415 TSR ..................... 124, 280, 402, 409, 416 TSTR........................... 127, 402, 409, 416 TSYR .......................... 128, 402, 409, 416 Reset state ................................................. 42 Reset-synchronized PWM mode............. 163 RISC.......................................................... 17 Serial communication interface............... 277 Single mode ............................................ 333 Single-cycle scan .................................... 335 Sleep mode.............................................. 395 Software standby mode........................... 396 Status Register (SR) .................................. 13 Synchronous operation............................ 142 System registers ........................................ 14 The functions of multiplexed pins........... 353 Trap instruction exception processing....... 62 Index Vector Base Register (VBR)..................... 14 Vector numbers......................................... 77 Vector table............................................... 77 Watchdog timer ...................................... 263 Watchdog Timer Mode ...........................269 Word .........................................................15 Writing to RSTCSR ................................274 Writing to TCNT and TCSR ...................273 Rev.2.00 Sep. 27, 2007 Page 447 of 448 REJ09B0394-0200 Index Rev.2.00 Sep. 27, 2007 Page 448 of 448 REJ09B0394-0200 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7101 Publication Date: 1st Edition, February, 2003 Rev.2.00, September 27, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 SH7101 Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
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